Cypress CY62138F manual AC Test Loads and Waveforms, Data Retention Waveform, Parameters Unit

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CY62138F MoBL®

AC Test Loads and Waveforms

R1

VCC

ALL INPUT PULSES

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

 

 

3.0V

 

 

 

 

 

 

 

 

90%

R2

10%

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rise Time = 1 V/ns

 

 

 

 

 

 

 

Equivalent to:

THEVENIN EQUIVALENT

OUTPUT

 

 

 

RTH

 

 

 

 

V

 

 

 

 

 

 

 

90%

10%

Fall Time = 1 V/ns

Parameters

5.0V

Unit

R1

1800

 

 

 

R2

990

 

 

 

RTH

639

VTH

1.77

V

Data Retention Characteristics (Over the Operating Range)

Parameter

Description

 

 

 

Conditions

Min

Typ [3]

Max

Unit

VDR

VCC for Data Retention

 

 

 

 

2.0

 

 

V

ICCDR [7]

Data Retention Current

VCC= VDR,

 

1

> VCC 0.2V or CE2 < 0.2V,

 

1

5

A

CE

 

 

VIN > VCC - 0.2V or VIN < 0.2V

 

 

 

 

tCDR [8]

Chip Deselect to Data

 

 

 

 

0

 

 

ns

 

Retention Time

 

 

 

 

 

 

 

 

tR [9]

Operation Recovery Time

 

 

 

 

tRC

 

 

ns

Data Retention Waveform [10]

 

 

VCC(min)

DATA RETENTION MODE

VCC(min)

V

CC

V

> 2.0V

 

tCDR

DR

 

tR

 

 

 

 

CE

 

 

 

 

Notes:

9.Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.

10.CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.

Document #: 001-13194 Rev. *A

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Contents Logic Block Diagram Functional Description FeaturesCypress Semiconductor Corporation Pin Configuration Product PortfolioPin SOIC/TSOP II Pinout Top View Max TypElectrical Characteristics Over the Operating Range Maximum RatingsOperating Range Thermal ResistanceData Retention Characteristics Over the Operating Range AC Test Loads and WaveformsData Retention Waveform Parameters UnitRead Cycle Parameter Description 45 ns Unit MinWrite Cycle Read Cycle No OE controlled 10, 16 Switching WaveformsWrite Cycle No WE controlled 10, 14, 18 Truth Table Inputs/Outputs Mode PowerOrdering Information Package Diagrams Pin 450 Mil Molded SoicPin Tsop II Issue Date Orig. Change Description of Change Document History