CY62148BN MoBL®
4-Mbit (512K x 8) Static RAM
Features
•High Speed
—70 ns
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•Low active power
—Typical active current: 2.5 mA @ f = 1 MHz
—Typical active current:12.5 mA @ f = fmax(70 ns)
•Low standby current
•Automatic
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•Easy memory expansion with CE and OE features
•CMOS for optimum speed/power
•Available in standard
Functional Description
The CY62148BN is a
Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18).
Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH for read. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
Logic Block Diagram |
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| INPUT BUFFER |
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| I/O0 |
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A0 |
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| I/O1 |
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A1 | DECODER |
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| I/O2 |
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A4 |
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A5 |
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| AMPS |
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A6 |
| 512K x 8 |
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| I/O3 |
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A7 |
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A | ROW |
| ARRAY |
| SENSE |
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A12 |
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| I/O4 |
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14 |
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A16 |
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A17 |
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| I/O5 |
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| COLUMN |
| POWER |
| I/O6 |
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CE |
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| DOWN |
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| DECODER |
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| I/O7 |
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WE |
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| 2 3 |
| 9 |
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OE |
| 15 18 13 8 A 11 10 |
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| A A A A A A | A A |
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Cypress Semiconductor Corporation | • | 198 Champion Court | • | San Jose, CA | • | ||||
Document #: |
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| Revised August 2, 2006 |
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