Cypress CY62148BN manual Features, Functional Description, Logic Block Diagram, A a a a

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CY62148BN MoBL®

4-Mbit (512K x 8) Static RAM

Features

High Speed

70 ns

4.5V–5.5V operation

Low active power

Typical active current: 2.5 mA @ f = 1 MHz

Typical active current:12.5 mA @ f = fmax(70 ns)

Low standby current

Automatic power-down when deselected

TTL-compatible inputs and outputs

Easy memory expansion with CE and OE features

CMOS for optimum speed/power

Available in standard lead-free and non-lead-free 32-lead (450-mil) SOIC, 32-lead TSOP II and 32-lead Reverse TSOP II packages

Functional Description

The CY62148BN is a high-performance CMOS static RAM organized as 512K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. This device has an automatic power-down feature that reduces power consumption by more than 99% when deselected.

Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18).

Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH for read. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.

The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW).

Logic Block Diagram

 

 

 

 

 

 

 

 

 

 

 

INPUT BUFFER

 

 

I/O0

 

 

 

 

 

 

 

 

 

A0

 

 

 

 

 

 

I/O1

 

 

A1

DECODER

 

 

 

 

 

I/O2

 

 

A4

 

 

 

 

 

 

 

A5

 

 

 

AMPS

 

 

 

 

A6

 

512K x 8

 

 

I/O3

 

 

A7

 

 

 

 

 

A

ROW

 

ARRAY

 

SENSE

 

 

 

 

A12

 

 

 

 

I/O4

 

 

14

 

 

 

 

 

 

 

 

 

A16

 

 

 

 

 

 

 

 

 

A17

 

 

 

 

 

 

I/O5

 

 

 

 

 

COLUMN

 

POWER

 

I/O6

 

 

CE

 

 

 

DOWN

 

 

 

 

 

 

DECODER

 

 

 

 

 

 

 

 

 

I/O7

 

 

WE

 

 

 

 

 

 

 

 

 

 

2 3

 

9

 

 

 

 

 

OE

 

15 18 13 8 A 11 10

 

 

 

 

 

 

A A A A A A

A A

 

 

 

 

 

Cypress Semiconductor Corporation

198 Champion Court

San Jose, CA 95134-1709

408-943-2600

Document #: 001-06517 Rev. *A

 

 

 

 

 

 

Revised August 2, 2006

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Contents Logic Block Diagram FeaturesFunctional Description Cypress Semiconductor CorporationProduct Portfolio Pin ConfigurationTsop CY62148BNLLMaximum Ratings Electrical Characteristics Over the Operating RangeOperating Range Capacitance462148BNLL-70 Parameter Description Unit Min Switching Characteristics5 Over the Operating RangeRead Cycle Write CycleSwitching Waveforms Data Retention Characteristics Over the Operating RangeData Retention Waveform Write Cycle No WE Controlled, OE High During Write13 Write Cycle No CE Controlled13Data I/O Data Valid Data I/O Data in ValidTruth Table 0-I/O Mode PowerOrdering Information Write Cycle No.3 WE Controlled, OE LOW13Dimensions in Inchesmm MIN Package DiagramsLead 450-Mil Molded Soic Lead Thin Small Outline Package Type IILead Reverse Thin Small Outline Package Type II REV ECN no Document HistoryNXR VKN