Cypress CY62146ESL manual Package Diagrams

Page 11

CY62146ESL MoBL→

Package Diagrams

51-85087-*A

Document #: 001-43142 Rev. **

Page 11 of 12

[+] Feedback

Image 11

Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesLogic Block Diagram Functional DescriptionProduct Portfolio Pin ConfigurationDevice Range Ambient Electrical CharacteristicsMaximum Ratings Operating RangeTsop CapacitanceThermal Resistance AC Test Loads and WaveformsParameter Description Conditions Min Typ Max Unit Data Retention CharacteristicsData Retention Waveform Write Cycle12 Switching CharacteristicsParameter Read Cycle Description 45 ns Min Max Unit Read Cycle No.1 Address Transition Controlled Switching WaveformsWrite Cycle No 1 WE Controlled 12, 16 Write Cycle 3 WE controlled, OE LOW CY62146ESL-45ZSXI Inputs/Outputs Mode PowerOrdering Information BHE BLEPackage Diagrams REV ECN no Issue Date Orig. Change Description of Change 1875228New Data Sheet Document History