Cypress CY62146ESL Switching Characteristics, Parameter Read Cycle Description 45 ns Min Max Unit

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CY62146ESL MoBL

Switching Characteristics

Over the Operating Range [9]

Parameter

Read Cycle

Description

45 ns

Min

Max

 

 

Unit

tRC

 

Read Cycle Time

45

 

ns

tAA

 

Address to Data Valid

 

45

ns

tOHA

 

Data Hold from Address Change

10

 

ns

tACE

 

 

 

 

LOW to Data Valid

 

45

ns

CE

tDOE

 

 

 

 

LOW to Data Valid

 

22

ns

OE

tLZOE

 

 

 

 

LOW to LOW-Z[10]

5

 

ns

OE

tHZOE

 

 

 

 

HIGH to High-Z[10, 11]

 

18

ns

OE

tLZCE

 

 

 

LOW to Low-Z[10]

10

 

ns

CE

tHZCE

 

 

 

HIGH to High-Z[10, 11]

 

18

ns

CE

tPU

 

 

 

LOW to Power Up

0

 

ns

CE

tPD

 

 

 

HIGH to Power Down

 

45

ns

CE

tDBE

 

 

 

 

 

 

 

 

 

22

ns

BLE/BHE LOW to Data Valid

tLZBE

 

 

 

 

 

 

 

 

5

 

ns

BLE/BHE LOW to Low-Z[10]

tHZBE

 

 

 

 

 

 

 

 

 

18

ns

BLE/BHE HIGH to HIGH-Z[10,11]

Write Cycle[12]

 

 

 

 

 

 

 

 

 

 

 

tWC

 

Write Cycle Time

45

 

ns

tSCE

 

 

 

LOW to Write End

35

 

ns

CE

tAW

 

Address Setup to Write End

35

 

ns

tHA

 

Address Hold from Write End

0

 

ns

tSA

 

Address Setup to Write Start

0

 

ns

tPWE

 

 

 

 

Pulse Width

35

 

ns

WE

tBW

 

 

 

 

 

 

 

 

35

 

ns

BLE/BHE LOW to Write End

tSD

 

Data Setup to Write End

25

 

ns

tHD

 

Data Hold from Write End

0

 

ns

tHZWE

 

 

 

 

LOW to High-Z[10, 11]

 

18

ns

WE

tLZWE

 

 

 

 

HIGH to Low-Z[10]

10

 

ns

WE

Notes

9.Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3V, and output loading of the specified IOL/IOH as shown in the AC Test Loads and Waveforms on page 4.

10.At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.

11.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.

12.The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.

Document #: 001-43142 Rev. **

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Contents Functional Description FeaturesLogic Block Diagram Cypress Semiconductor Corporation 198 Champion CourtPin Configuration Product PortfolioOperating Range Electrical CharacteristicsMaximum Ratings Device Range AmbientAC Test Loads and Waveforms CapacitanceThermal Resistance TsopData Retention Characteristics Data Retention WaveformParameter Description Conditions Min Typ Max Unit Switching Characteristics Parameter Read Cycle Description 45 ns Min Max UnitWrite Cycle12 Switching Waveforms Read Cycle No.1 Address Transition ControlledWrite Cycle No 1 WE Controlled 12, 16 Write Cycle 3 WE controlled, OE LOW BHE BLE Inputs/Outputs Mode PowerOrdering Information CY62146ESL-45ZSXIPackage Diagrams Document History Issue Date Orig. Change Description of Change 1875228New Data Sheet REV ECN no