Cypress CY7C1298H manual Document History, Issue Date Orig. Description of Change

Page 16

CY7C1298H

Document History Page

Document Title: CY7C1298H 1-Mbit (64K x 18) Pipelined DCD Sync SRAM

Document Number: 38-05665

REV.	ECN NO.	Issue Date	Orig. of	Description of Change
REV.	ECN NO.	Issue Date	Change	Description of Change

**	343896	See ECN	PCI	New Data Sheet

*A	430678	See ECN	NXR	Changed address of Cypress Semiconductor Corporation on Page# 1 from
				“3901 North First Street” to “198 Champion Court”
				Added 2.5VI/O option
				Changed Three-State to Tri-State
				Included Maximum Ratings for VDDQ relative to GND
				Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
				Electrical Characteristics Table
				Modified test condition from VIH < VDD to VIH < VDD
				Replaced Package Name column with Package Diagram in the Ordering
				Information table
*B	481916	See ECN	VKN	Converted from Preliminary to Final.
				Updated the Ordering Information table.

Document #: 38-05665 Rev. *B

Page 16 of 16

[+] Feedback

Image 16

Contents Features Selection Guide Functional Description1166 MHz 133 MHz Unit Cypress Semiconductor CorporationFunctional Block Diagram CY7C1298HCY7C1298H Pin Configurations Pin TqfpTop View Pin Descriptions Functional Overview Sleep ModeBurst Sequences Interleaved ‘Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDFirst Second Third Fourth Address A1, A0Function ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Electrical Characteristics Over the Operating Range7,8 Maximum RatingsOperating Range Ambient RangeCapacitance9 Thermal Characteristics9AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 14 Switching Waveforms Read Timing16Write Timing16 Address A1 A2Read/Write Timing16, 18 ZZ Mode Timing20 DON’T CareOrdering Information Package DiagramPin Tqfp 14 x 20 x 1.4 mm Issue Date Orig. Description of Change Document History