Connect Tech Inc. FreeForm/Express S6 - PCIe
FPGA Design
In general, FPGA designs developed for the FreeForm/Express S6 can be based on IP generated with Xilinx’s CORE Generator. The following table lists the CORE Generator IP proven to be compatible, along with their current versions numbers.
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Memory | MIG | 3.6 |
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Rocket I/O | 1.7 |
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Transceiver Wizard |
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PCIe | 1.4 |
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Block for PCI Express |
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Ethernet | Tri Mode Ethernet MAC | 4.4 | A valid license is required to use this IP, contact Xilinx |
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For the latest reference designs developed by Connect Tech Inc., visit http://devel.connecttech.com
Revision 0.01 | 18 |