82C55A
Pin Description
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SYMBOL | NUMBER | TYPE | DESCRIPTION | |||||||||
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VCC | 26 |
| VCC: The +5V power supply pin. A 0.1μF capacitor between pins 26 and 7 is | |||||||||
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| recommended for decoupling. | ||||
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GND | 7 |
| GROUND | |||||||||
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I/O | DATA BUS: The Data Bus lines are bidirectional | |||||||||||
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| system data bus. | ||||
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RESET | 35 | I | RESET: A high on this input clears the control register and all ports (A, B, C) are set | |||||||||
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| to the input mode with the “Bus Hold” circuitry turned on. | ||||
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| 6 | I | CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the | ||||
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| CS | ||||||||||
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| Data Bus for CPU communications. | ||||
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| 5 | I | READ: Read is an active low input control signal used by the CPU to read status | ||||
| RD | |||||||||||
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| information or data via the data bus. | ||||
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| 36 | I | WRITE: Write is an active low input control signal used by the CPU to load control | ||||
| WR | |||||||||||
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| words and data into the 82C55A. | ||||
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8, 9 | I | ADDRESS: These input signals, in conjunction with the |
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RD | WR | |||||||||||
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| the selection of one of the three ports or the control word register. A0 and A1 are | ||||
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| normally connected to the least significant bits of the Address Bus A0, A1. | ||||
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| I/O | PORT A: | ||||||||||
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| present on this port. | ||||
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I/O | PORT B: | |||||||||||
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I/O | PORT C: | |||||||||||
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Functional Diagram
POWER | +5V |
| GROUP A | I/O | |
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| PORT A | |||
SUPPLIES | GND | GROUP A | |||
(8) |
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| CONTROL |
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| GROUP A | I/O |
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| PORT C | |
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| UPPER | ||
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DATA BUS |
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| (4) |
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| DATA BUS |
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BUFFER |
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| GROUP B |
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| I/O | ||
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| INTERNAL | PORT C | |
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| DATA BUS | LOWER | |
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| (4) |
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RD | READ |
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WR | GROUP B |
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WRITE |
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A1 | CONTROL | CONTROL | GROUP B | I/O |
LOGIC |
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A0 |
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| (8) |
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RESET |
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CS |
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2