82C55A
Functional Description
I/O
PA7-
Data Bus Buffer
This
POWER | +5V | GROUP A |
SUPPLIES | GND | |
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| CONTROL |
GROUP A
PORT A
(8)
PA0
I/O
received by the buffer upon execution of input or output instructions by the CPU. Control words and status informa- tion are also transferred through the data bus buffer.
Read/Write and Control Logic
The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups.
(CS) Chip Select. A “low” on this input pin enables the communcation between the 82C55A and the CPU.
(RD) Read. A “low” on this input pin enables 82C55A to send
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DATA BUS |
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BUS |
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BUFFER | |||
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| DATA BUS | |
RD | READ | GROUP B | |
WR | |||
WRITE | |||
A1 | CONTROL | ||
CONTROL | |||
A0 |
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LOGIC |
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RESET |
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CS |
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PC7-
GROUP A PC4 PORT C
UPPER
(4)
I/O
PC3-
GROUP B | PC0 |
PORT C |
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LOWER |
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(4) |
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| PB7- |
GROUP B | PB0 |
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PORT B |
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(8) |
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the data or status information to the CPU on the data bus. In essence, it allows the CPU to “read from” the 82C55A.
(WR) Write. A “low” on this input pin enables the CPU to write data or control words into the 82C55A.
(A0 and A1) Port Select 0 and Port Select 1. These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register. They are normally connected to the least significant bits of the address bus (A0 and A1).
82C55A BASIC OPERATION
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| INPUT OPERATION |
A1 | A0 | RD | WR | CS | (READ) |
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0 | 0 | 0 | 1 | 0 | Port A → Data Bus |
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0 | 1 | 0 | 1 | 0 | Port B → Data Bus |
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1 | 0 | 0 | 1 | 0 | Port C → Data Bus |
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1 | 1 | 0 | 1 | 0 | Control Word → Data Bus |
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| OUTPUT OPERATION |
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0 | 0 | 1 | 0 | 0 | Data Bus → Port A |
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0 | 1 | 1 | 0 | 0 | Data Bus → Port B |
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1 | 0 | 1 | 0 | 0 | Data Bus → Port C |
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1 | 1 | 1 | 0 | 0 | Data Bus → Control |
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| DISABLE FUNCTION |
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X | X | X | X | 1 | Data Bus → |
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X | X | 1 | 1 | 0 | Data Bus → |
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FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER, READ/WRITE, GROUP A & B CONTROL LOGIC FUNCTIONS
(RESET) Reset. A “high” on this input initializes the control register to 9Bh and all ports (A, B, C) are set to the input mode. “Bus hold” devices internal to the 82C55A will hold the I/O port inputs to a logic “1” state with a maximum hold current of 400μA.
Group A and Group B Controls
The functional configuration of each port is programmed by the systems software. In essence, the CPU “outputs” a con- trol word to the 82C55A. The control word contains information such as “mode”, “bit set”, “bit reset”, etc., that ini- tializes the functional configuration of the 82C55A.
Each of the Control blocks (Group A and Group B) accepts “commands” from the Read/Write Control logic, receives “control words” from the internal data bus and issues the proper commands to its associated ports.
Control Group A - Port A and Port C upper (C7 - C4)
Control Group B - Port B and Port C lower (C3 - C0)
The control word register can be both written and read as shown in the “Basic Operation” table. Figure 4 shows the control word format for both Read and Write operations. When the control word is read, bit D7 will always be a logic “1”, as this implies control word mode information.
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