82C55A
CONTROL WORD
D7 D6 D5 D4 D3 D2 D1 D0
1 1 1/0 1/0 1/0
1 = INPUT
0 = OUTPUT
PORT B
1 = INPUT
0 = OUTPUT
WR
GROUP B MODE 0 = MODE 0
1 = MODE 1
RD
FIGURE 11. MODE CONTROL WORD
|
| PC3 | INTRA |
| 8 | ||
|
| PC7 | OBFA |
INTE | PC6 | ACKA | |
1 |
| ||
|
|
| |
INTE | PC4 | STBA | |
2 |
| ||
|
|
| |
|
| PC5 | IBFA |
| 3 | ||
| I/O | ||
|
|
|
FIGURE 12. MODE 2
DATA FROM
CPU TO 82C55A
WR
OBF
INTR
ACK
STB
IBF
PERIPHERAL BUS
RD
tWOB
tST
tSIB
tPS
tPH
DATA FROM
PERIPHERAL TO 82C55A
tAOB
tAK
tAD
tKD
tRIB
DATA FROM
82C55A TO PERIPHERAL
DATA FROM
82C55A TO CPU
NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. (INTR = IBF ∙ MASK ∙ STB ∙ RD ÷ OBF ∙ MASK ∙ ACK ∙ WR)
FIGURE 13. MODE 2 (BI-DIRECTIONAL)
11