SOYO SY-K7VTA manual Chipset Features, Spd

BIOS Setup Utility SY-K7VTA

After you have completed the changes, press [Esc] and follow the

instructions on your screen to save your settings or exit without saving.

The following table describes each field in the Advanced Chipset Features

Menu and how to configure each parameter.

3-4.1 CHIPSET FEATURES SETUP

CHIPSET FEATURES

DRAM Timing By

SPD

Setting	Description	Note
Disabled	If enable the DRAM will auto
Enabled	detect the DRAM timing	Default

DRAM Clock

SDRAM Cycle Length

100MHz	This item allows you to control the	Default
133MHz	DRAM speed.
3	When synchronous DRAM is	Default

2installed, the number of clock cycles of CAS latency depends on the DRAM timing. Do not reset this field from the default value specified by the system designer.

Bank Interleave

Disabled	Increase DRAM performance.	Default
Enabled

Memory Hole	Disabled		Default
	Enabled	Some interface cards will map
		their ROM address to this area. If
		this occurs, select [Enabled] in this
		field.
PCI master
	Disabled	Disabled/Enabled PCI Master
Pipeline Req	Enabled	Pipeline Req.	Default

P2C/C2P Concurrency

Disabled	This item allows you to
Enabled	enable/disable the PCI to CPU,	Default
	CPU to PCI concurrency.

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