SOYO SY-K7VTA manual PCI Delay Transaction Setting Description, PCI#2 Access #1 Retry

BIOS Setup Utility SY-K7VTA

CHIPSET FEATURES SETUP (Continued)

CHIPSET FEATURES

PCI Delay Transaction

Setting	Description	Note
Disabled	The chipset has an embedded 32-bit
Enabled	posted write buffer to support delay	Default
	transactions cycles. Select Enabled

to support compliance with PCI specification version 2.1.

PCI#2 Access #1 Retry

Disabled

Enabled

When disabled, PCI#2 will not be

disconnected until access finishes Default (difault). When enabled, PCI#2 will

be disconnected if max retries are attempted without success.

AGP Master 1 WS Write

Disabled		Default
Enabled	When Enabled, writes to the
	AGP(Accelerated Graphics Port) are
	executed with one wait states.

AGP Master 1 WS Read

Disabled		Default
Enabled	When Enabled, read to the AGP
	(Accelerated Graphics Port) are
	executed with one wait states.

67