BIOS Setup Utility
CHIPSET FEATURES SETUP (Continued)
| CHIPSET |
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| Setting | Description | Note |
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| FEATURES |
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PCI Delay Transaction
| Disabled | The chipset has an embedded |
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| Enabled | posted write buffer to support delay | Default |
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| transactions cycles. Select Enabled |
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to support compliance with PCI specification version 2.1.
PCI#2 Access #1 Retry
| Disabled | When disabled, PCI#2 will not be |
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| Enabled | disconnected until access finishes | Default |
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| (difault). When enabled, PCI#2 will |
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be disconnected if max retries are attempted without success.
AGP Master 1 WS Write
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Disabled |
| Default |
Enabled | When Enabled, writes to the |
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| AGP(Accelerated Graphics Port) are |
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| executed with one wait states. |
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AGP Master 1 WS Read
Disabled |
| Default |
Enabled | When Enabled, read to the AGP |
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| (Accelerated Graphics Port) are |
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| executed with one wait states. |
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