SOYO SY-7IZB+ manual Cmos Clearing JP5, Set JP9 for power up FSB clock and AGP bus clock, Setting

Hardware Setup SY-7IZB+

Step 14. CMOS Clearing (JP5)

After you have turned off your computer, clear the CMOS memory by momentarily shorting pins 2-3 on jumper JP5, for a few seconds. Then restore JP5 to the initial 1-2 jumper setting in order to recover and retain the default settings.

Jumper JP5 can be easily identified by its white colored cap.

CMOS Clear CMOS Data Retain CMOS Data Clearing

JP5

Setting

Short pin 2-3 for

at least 5 seconds to clear the CMOS

1

2

3

Short pin 1-2 to retain new settings

1

2

3

Note: You must unplug the ATX power cable from the ATX power connector when performing the CMOS Clear operation.

Step 15. Set JP9 for power up FSB clock and AGP bus clock.

JP9 is used to adjust AGP bus clock frequency depending on the value of the front side bus (FSB) clock, also the setting of the JP9 determines the power up FSB clock which will remain effective until the BIOS set the FSB clock to the CMOS setting.

	1		1
JP9 Setting	2		2
	3		3
Power up FSB	66MHz		100MHz
Clock
AGP Clock	AGP Clock =		AGP Clock =
	FSB Clock	÷ 1	FSB Clock ÷ 1.5

Note: The specification of maximum AGP bus Clock frequency

is 66.6MHz.

∗Set JP9 to pin 1-2 short when you use a FSB 100MHz CPU.

∗Set JP9 to pin 2-3 short when you use a FSB 66MHz CPU.

∗Set JP9 to pin 1-2 short when you use a FSB 66MHz CPU but want to over clock the FSB clock to 100MHz via the BIOS setting.

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