
Users Manual TOPAS900 Flash V2.1
5.1.1.MCU Internal Memory Map ______________________________________________ 30
5.1.2.Internal Mapping in different Modes ________________________________________ 31
5.1.3.Programming in Single Boot Mode _________________________________________ 31
5.1.4.Normal Operation Mode _________________________________________________ 32
5.2.Jumper Description _________________________________________________ 34
5.2.1.The jumpers of the 
5.2.2.The jumpers of the Flash Carrier Board ______________________________________ 34
5.3.Programming of Flash Memory _______________________________________ 34
6.Technical Sheets_________________________________________________ 36
6.1.Board Schematics ___________________________________________________ 36
6.2.Component Print ___________________________________________________ 41
6.3.PCB Routing_______________________________________________________ 42
7.Application Board _______________________________________________ 43
8.Electromagnetic Compatibility______________________________________ 45
Figures | 
  | 
Figure 1 : The TOPAS900 Flash Board (Top View) | 8  | 
Figure 2 : Breaking off TOPAS900 Flash Board from Flash Carrier Board | 9  | 
Figure 3 : Principe of Connection | 9  | 
Figure 4 : TMP95FY64 Schematic Block Diagram | 13  | 
Figure 5 : IAR Embedded Workbench Desktop with Project Window | 17  | 
Figure 6 :  | 19  | 
Figure 7 : TMPro Window | 22  | 
Figure 8 : Memory Usage of IAR  | 27  | 
Figure 9 : Memory Usage of Toshiba  | 28  | 
Figure 10 : The MCU's Internal Memory Map | 30  | 
Figure 11 : Internal Mapping in Single Boot and Single Chop Mode | 31  | 
Figure 12 : Map for Internal Flash Programming | 32  | 
Figure 13 : Memory Map for using external / internal Flash | 33  | 
Figure 14 : Flash Programmer Window | 35  | 
Figure 15 : Schematic Page 1 of 4 | 37  | 
Figure 16 : Schematic Page 2 of 4 | 38  | 
Figure 17 : Schematic Page 3 of 4 | 39  | 
Figure 18 : Schematic Page 4 of 4 | 40  | 
Figure 19 : Component Print – Top & Bottom View | 41  | 
Figure 20 : PCB Routing – Top & Bottom View | 42  | 
Figure 21 : The Application Board | 43  | 
HWU Elektronik Oberhausen  | Page 4  |