Clevo D900F B.Schematic Diagrams, ChannelB, DDR3 Channel B SO-DIMM1 B, Layout note, C Hc

DDR3 Channel B SO-DIMM_1

Schematic Diagrams

ChannelB

SO-DIMM1

M_MAA_B0

98

JD IMM2A

5

M_D ATA_B0

A0

DQ0

M_MAA_B1

97

7

M_D ATA_B1

A1

DQ1

M_MAA_B2

96

15

M_D ATA_B2

A2

DQ2

M_MAA_B3

95

17

M_D ATA_B3

A3

DQ3

M_MAA_B4

92

4

M_D ATA_B4

A4

DQ4

M_MAA_B5

91

6

M_D ATA_B5

M_MAA_B6

90

A5

DQ5

16

M_D ATA_B6

A6

DQ6

M_MAA_B7

86

18

M_D ATA_B7

Layout Note:

A7

DQ7

M_MAA_B8

89

21

M_D ATA_B8

A8

DQ8

M_MAA_B9

85

23

M_D ATA_B9

CLK0/space/CLK_1

M_MAA_B1 0

107

A9

DQ9

33

M_D ATA_B10

A10/AP

DQ10

M_MAA_B1 1

84

35

M_D ATA_B11

MS:8.5 / 5 / 8.5

M_MAA_B1 2

83

A11

DQ11

22

M_D ATA_B12

A12/BC #

DQ12

M_MAA_B1 3

119

24

M_D ATA_B13

SL: 4 / 4 / 4

A13

DQ13

M_MAA_B1 4

80

34

M_D ATA_B14

M_MAA_ B15

78

A14

DQ14

36

M_D ATA_B15

A15

DQ15

39

M_D ATA_B16

DQ16

M_SBS_ B0

109

BA0

41

M_D ATA_B17

DQ17

M_SBS_ B1

108

51

M_D ATA_B18

M_SBS_ B2

79

BA1

DQ18

53

M_D ATA_B19

BA2

DQ19

M_SCS_B_ N0

114

40

M_D ATA_B20

M_SCS_B_ N1

121

S0#

DQ20

42

M_D ATA_B21

S1#

DQ21

D IM0

C HA

C HB

C HC

CK_ M_C H1_0_DP

101

C K0

DQ22

50

M_ DATA_B22

CK_ M_C H1_0_DN

103

52

M_ DATA_B23

CK_ M_C H1_1_DP

102

C K0 #

DQ23

57

M_ DATA_B24

S A0

Low

Lo w

Hi gh

C K1

DQ24

CK_ M_C H1_1_DN

104

59

M_ DATA_B25

C K1 #

DQ25

73

67

M_ DATA_B26

M_SCKE_B0

C KE0

DQ26

M_SCKE_B1

74

69

M_ DATA_B27

S A1

Low

Hig h

L ow

C KE1

DQ27

M_CAS_B_ N

115

56

M_ DATA_B28

C AS#

DQ28

M_RAS_B_ N

110

58

M_ DATA_B29

M_WE_B_ N

113

R AS#

DQ29

68

M_ DATA_B30

W E#

DQ30

SA0_ DIM1

197

70

M_ DATA_B31

SA0

DQ31

SA1_ DIM1

201

SA1

DQ32

12 9

M_ DATA_B32

SCL K

202

SCL

DQ33

13 1

M_ DATA_B33

SDATA

200

SDA

DQ34

14 1

M_ DATA_B34

R276

R277

14 3

M_ DATA_B35

M_OD T_B0

DQ35

116

O DT0

13 0

M_ DATA_B36

DQ36

10K_04

10K_04

M_OD T_B1

120

13 2

M_ DATA_B37

O DT1

DQ37

DQ38

14 0

M_ DATA_B38

R 27 2

0 _0 4

Z0804

11

D M0

DQ39

14 2

M_ DATA_B39

R 26 6

0 _0 4

Z0805

28

14 7

M_ DATA_B40

D M1

DQ40

3VS

R 26 7

0 _0 4

Z0806

46

14 9

M_ DATA_B41

D M2

DQ41

R 27 3

0 _0 4

Z0807

63

15 7

M_ DATA_B42

D M3

DQ42

R 26 4

0 _0 4

Z0808 136

15 9

M_ DATA_B43

D M4

DQ43

R

27 4

0 _

0 4

Z08

09

153

14 6

M_ DATA_B44

D M5

DQ44

R

26 5

0 _

0 4

Z08

10

170

14 8

M_ DATA_B45

D M6

DQ45

R

27 5

0 _

0 4

Z08

11

187

15 8

M_ DATA_B46

D M7

DQ46

16 0

M_ DATA_B47

M _DQ S_ A_D P8

DQ47

M_DQS_B_DP0

12

D QS0

16 3

M_ DATA_B48

DQ48

M_DQS_B_DP1

29

16 5

M_ DATA_B49

M _DQ S_ A_D N8

D QS1

DQ49

M_DQS_B_DP2

47

17 5

M_ DATA_B50

X 58

?

?

? ?

D QS2

DQ50

M_DQS_B_DP3

64

17 7

M_ DATA_B51

D QS3

DQ51

M_DQS_B_DP4

137

16 4

M_ DATA_B52

?

?

?

EC C? ? ,

D QS4

DQ52

M_DQS_B_DP5

154

16 6

M_ DATA_B53

?

?

D M

? ? ? ? ? OK

D QS5

DQ53

M_DQS_B_DP6

171

17 4

M_ DATA_B54

D QS6

DQ54

M_DQS_B_DP7

188

17 6

M_ DATA_B55

D QS7

DQ55

18 1

M_ DATA_B56

M_DQS_B_DN 0

DQ56

10

D QS0#

18 3

M_ DATA_B57

DQ57

M_DQS_B_DN 1

27

19 1

M_ DATA_B58

D QS1#

DQ58

M_DQS_B_DN 2

45

19 3

M_ DATA_B59

D QS2#

DQ59

M_DQS_B_DN 3

62

18 0

M_ DATA_B60

M_DQS_B_DN 4

135

D QS3#

DQ60

18 2

M_ DATA_B61

D QS4#

DQ61

JDI MM2B

1.5V

75

VDD1

VSS16

76

VDD2

VSS17

81

VDD3

VSS18

82

VDD4

VSS19

87

VDD5

VSS20

88

3VS

VDDSPD B

93

VDD6

VSS21

94

VDD7

VSS22

NC 1

VDD8

VSS23

99

100

VDD9

VSS24

105

VDD10

VSS25

106

VDD11

VSS26

NC _04

VDD12

VSS27

111

VDD13

VSS28

112

VDD14

VSS29

117

118

VDD15

VSS30

VDD16

VSS31

123

VD DSPDB

124

VDD17

VSS32

20 mil s

tra ce

VDD18

VSS33

199

VSS34

VDDSPD

VSS35

C473

C4 74

Z0801

77

VSS36

NC 1

VSS37

Z0802

122

2. 2U _16 V_X5 R_ 06

. 1U_ 10V_X7R_04

Z0803

125

NC 2

VSS38

NC TEST

VSS39

PM_EXTTS_ DD R#

198

EVEN T#

VSS40

DD R1_DRAMRST

30

VSS41

RESET#

VSS42

VSS43

1

VSS44

VREF_D Q

VSS45

DIMM_C A_VREF_B

126

VREF_C A

VSS46

VSS47

2

VSS48

VSS1

VSS49

3

VSS2

VSS50

8

VSS3

VSS51

9

VSS4

VSS52

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26

VTT1

VSS10

31

VSS11

VTT2

32

VSS12

37

G1

38

VSS13

VSS14

G2

43

VSS15

D DR 3_SODIMM1_20 4P

44

48

49

54

55

60

61

65

66

71

72

127

128

133

134

138

139

144

145

150

151

155

156

161

162

167

168

172

173

178

179

184

185

189

190

195

196

0. 75 V

203

204

GND 1

GND 2

M_DATA_B[6 3: 0]	M_ DATA_B[63 :0]			2
M _C B_E CC _B[ 7: 0]
M_DQS_B_D P[7: 0]	M_ DQS_ B_DP[ 7: 0]			2
M_DQS_B_D N[ 7:0]
	M_ DQS_ B_DN [7:0]			2
M_MAA_B[ 15 :0]
	M_MAA_ B[1 5:0 ] 3
M_SBS_B[2:0 ]
	M_SBS_B[ 2:0]		3
M_SCKE_B[ 1: 0]
	M_SC KE_B[1: 0]		3
M_OD T_B[ 1: 0]
	M_ODT_ B[1 :0]		3
C K_M_ CH1_0 _DP
	CK_M_CH 1_0 _D P 3
C K_M_ CH1_0 _DN
	CK_M_CH 1_0 _D N 3
C K_M_ CH1_1 _DP
	CK_M_CH 1_1 _D P 3
C K_M_ CH1_1 _DN
	CK_M_CH 1_1 _D N 3
M_RAS_B_ N
	M_R AS_ B_N 3
M_CAS_B_ N
	M_C AS_ B_N 3
M_WE_ B_N
	M_W E_ B_N 3
M_SCS_B_ N0
	M_SC S_ B_N0 3
M_SCS_B_ N1
	M_SC S_ B_N1 3
D DR1_D RAMR ST
	DDR 1_D RAMR ST			3
PM_EXTTS_D DR#
	PM_EXTTS_DD R#			7,9
SC LK
	SC LK	7, 9, 12, 16 ,18 ,19,32
SD ATA
	SDATA	7 ,9, 12,1 6,1 8, 19, 32

Sheet 8 of 47

DDR3 Channel B

SO-DIMM_1

B.Schematic Diagrams

M_DQS_B_DN 5

152

D QS5#

DQ62

19 2

M_ DATA_B62

M_DQS_B_DN 6

169

19 4

M_ DATA_B63

D QS6#

DQ63

M_DQS_B_DN 7

186

D QS7#

DD R3_SODI MM1_204P

1.5V

R2 71

15m il s t rac e

Fr om po wer 0 .75 V

1K_ 1%_0 4

34m il s s pac in g

0 .75 V

DI MM_ CA_VR EF_B

R2 70

C 469

C1 38

C 11 3

C1 45

C114

1K_ 1%_0 4

.1U _1 0V_X7R_ 04

4. 7U_ 6. 3V_06

4 .7U_6 .3V_06

.1U _10V_X7R_04

. 1U_10V_X7 R_04

Layout note:SO-DIMM_1 is placed farther from the CPU than SO-DIMM_0

CLOSE TO SO-DIMM_1

4, 5, 7,9 ,40,4

3

1. 5V

7,9 ,12, 13, 15 ..30, 32 ,39 ,41,4

3

3VS

1.5 V

7,9,4 0

0. 75 V

+ C1 49

C12

0

C 136

C117

C1 18

C14 2

C 14 0

C1 37

C141

C 115

C139

C 116

C1 19

100U _6.3V_ B

10U_

10V_ 08

10U_1

0V_ 08

10U_ 10V_08

10U_10V_ 08

10 U_10V_0 8

*1 0u_10V_0 8

. 1U_10V_X7 R_04

. 1U _10V_X7 R_ 04

1 U_6.3 V_04

.01U_ 16 V_X7R_04

.1 U_10V_X7R _04

.1 U_ 10V_X7R _0 4

DDR3 Channel B SO-DIMM_1 B - 9