Clevo D900F Intel Debug Card & Fan Control, Schematic Diagrams, Sheet 18 of, Cpu Fan Control

Intel Debug Card & Fan Control

Intel Debug Card

CPU FAN CONTROL

Schematic Diagrams

? ? ? ? ? ? ? ? , ? ? QPI? ? ? Intel ? ? ? ?External Connection

5VS_CFAN 5VS	C PU_FON # 1		U 12		8
		2	FON	GND	7
		3	VI N	GND	6
		4	VOUT	GND	5
28 CPU_FAN			VSET	GND

C PU _FON#

R233

*0_04

4 H_MBP_N[7:0]

4 H_PRD Y_N

4 H_PREQ_N

4 H_TCK

4 H_TDI

4 H_TDO

4 H_TMS

4 H_TRST_N

4 CPU_TAPGOOD

4CK_H _BCLK_ITP_DN

4CK_H _BCLK_ITP_DP

7..9,12,16,19,32 SDATA

7. .9, 12, 16,19,32 SC LK

	1	2	EXT_TBG_AK36
4,1	2,1	6	H_PWR GD
1	2,1	6	ICH _VRM_PWRGD

H_MBP_N[7:0]

H_PRD Y_N

H_PREQ_N

H_TCK

H_TDI

H_TDO

H_TMS

H_TRST_N

CPU_TAPGOOD

CK_H_BCLK_I TP_D N CK_H_BCLK_I TP_D P

SDATA

SCLK

EXT_TBG_AK36

H_PWR GD

ICH _VRM_PWRGD

CPU_VTT		XDP1
	43	VC C_OBS_AB	TCK1	55	H_TCK
	44			57
		VC C_OBS_CD	TCK0	52	H_TDO
H_PREQ_N	3		TDO	54	H_TRST_N
H_PRD Y_N	5	OBSFN _A0	TRSTN	56	H_TDI
H_MBP_N0	9	OBSFN _A1	TDI	58	H_TMS
		OBSD ATA_A_0	TMS
H_MBP_N1	11
H_MBP_N2	15	OBSD ATA_A_1	H OOK0	39	PRI_PW RGD_XDP
		OBSD ATA_A_2
H_MBP_N3	17			41	CPU_H OOK1_XDP
		OBSD ATA_A_3	H OOK1
				45	CPU_TAPGOOD
	21		H OOK2
				47
	23	OBSFN _B0	H OOK3	40	CK_H_BCLK_I TP_D P
H_MBP_N4		OBSFN _B1	ITPC LK/H OOK4
	27			42	CK_H_BCLK_I TP_D N
H_MBP_N5	29	OBSD ATA_B_0	ITPCLK*/H OOK5	46	FPGA_H_C PU RST	_N
H_MBP_N6	33	OBSD ATA_B_1	RESET*/H OOK6	48	HWRST#
H_MBP_N7	35	OBSD ATA_B_2	DBR*/H OOK7
		OBSD ATA_B_3	GND	1
SDATA	51			7
		SD A	GND
SCLK	53			13
		SC L	GND
				19
			GND
EXT_TBG_AK36	4			25
		OBSFN _C0	GND

	APE8872
5VS	5VS_CFAN
	C385

C383

.1U _16V_04

10U _10V_08

28 C PU _FANSEN

3VS	R1	4.7K_04
	C	A
	D 2	SC S355V

	J_CPUFAN1		J _C PUF AN1
	1
	2		3
	3		1
8520		5-03001

Sheet 18 of 47

B.

4,12	H_C PU RST#
4,16	HWRST#

H_C PU RST#

HWR ST#

6	OBSFN _C1	GND	31
10			37
12	OBSD ATA_C_0	GND	49
16	OBSD ATA_C_1	GND	59
18	OBSD ATA_C_2	GND	2
	OBSD ATA_C_3	GND	8
		GND
22			14
	OBSFN _D0	GND
24			20
	OBSFN _D1	GND
28			26
30	OBSD ATA_D_0	GND	32
	OBSD ATA_D_1	GND
34			38

SYS FAN CONTROL

5VS_SFAN 5VS		1	U 13		8
	SY S_FON#		FON	GND			SYS_FON#
		2	VI N	GND	7
		3			6			R234
		4	VOUT	GND	5	*0_04
28 SY S_FAN			VSET	GND

Intel Debug Card &

Fan Control

Schematic

H_PWRGD	R 251	1K_04	PRI_PW RGD _XDP
I CH_VR M_PWRGD R 249		0_04 CPU_HOOK1_XDP
H_CPURST#	R 250	1K_04	FPGA_H_C PURST_N

36	OBSD ATA_D_2	GND	50
	OBSD ATA_D_3	GND	60
		GND_XDP_PRESENT*
	*XDP

APE8872
5VS	5VS_SFAN
	J _SYSFAN 1

VGA FAN CONTROL

5VS_VFAN 5VS		VGA_FON# 1		U10		8
			2	FON	GND	7
			3	VI N	GND	6
				VOUT	GND
28 VGA_FAN		4				5
				VSET	GND
				APE8872
VGA_FON #
	R230

		C386					1
					C384		2
		.1U_16V_04			10U_10V_08		3	03001
				85205-
					SYS_FANSEN	3	J _SY SFA N1
	R2			*4.7K_04
3VS						1
	C		A
	D 1			*SCS355V

RAM FAN CONTROL

5VS_RFAN 5VS	R AM_FON # 1		U 25		8		R AM_FON#
			FON	GND
	2				7
		3	VI N	GND	6			R411
			VOUT	GND
28 R AM_FAN	4				5	*0_04
			VSET	GND
			APE8872
					5VS	5VS_RFAN

J _DDR FAN 1

Diagrams

*0_04
5VS	5VS_VFAN
	C381
	. 1U_16V_04	C 382

10U_10V_08

28 VGA_FANSEN

3VS	R232	4. 7K_04
	C	A
	D11	SCS355V

J_VGAFAN1

1

2

3

85205-03001

J_V GAF AN1

3

1

				C585
				.1U_16V_04			C178
28 RAM_FANSEN							10U_10V_08
	3VS	R349				4.7K_04
C				A
		D	23		SCS355V

12,17,20..23, 27, 29. .31,43				5V S
4,5, 15	, 39	, 44	CPU_V TT
7.. 9,12,13,15..17,19.. 30,3	2,3	9,4	1,43	3V S

1

2

3

85205-03001

J _DD RFA N1 3

1

Intel Debug Card & Fan Control B - 19