AMD 64 manual Hop

Page 27

40555 Rev. 3.00 June 2006

Performance Guidelines for AMD Athlon™ 64 and AMD Opteron™

 

ccNUMA Multiprocessor Systems

Here the same two foreground threads as before were run though the cases as before—local, crossfire and no crossfire. In addition, four background threads are left running on:

Node 0 (Core 1)

Node 1 (Core 1)

Node 2 (Core 0)

Node 3 (Core 0)

Each of these background threads read a local 64 MB array and the rate of memory demand of each of these threads is varied from low to very high simultaneously. A low rate of memory demand implies that each of the background threads is demanding a memory bandwidth of 0.5 GB/s. A very high rate of memory demand implies that each of the background threads is demanding a memory bandwidth of 4 GB/s as shown in Table 1 on page 16.

Even with the background threads, there are still some free cores left in the system. We call this a highly subscribed condition.

This allows us to study the impact of the background load on the foreground threads.

As shown in Figure 7 and Figure 8 on page 28, under both low and very high loads and high subscription, we still observe that the worst performance scenario occurs when write-only threads fire at each other (crossfire).

LOW: Total Time for both threads (write-write)

2.2

2

1.8

1.6

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1

0.8

0.6

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0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

136%

144%

 

 

 

 

 

 

 

113%

1 Hop

1 Hop

 

 

 

 

 

 

 

0 Hop

 

 

 

 

 

 

1 Hop

1 Hop

 

 

 

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NO

Xfire

 

 

 

 

 

 

 

Xfire

 

 

 

 

 

 

 

 

 

 

 

 

 

0.0.w.0 1.0.w.1 (0 Hops) (0 Hops)

0.0.w.1 1.0.w.3 (1 Hops) (1 Hops)

0.0.w.1 1.0.w.0 (1 Hops) (1 Hops)

Figure 7. Crossfire 1 Hop-1 Hop Case vs No Crossfire 1 Hop-1 Hop Case under a Low Background Load (High Subscription)

Chapter 3

Analysis and Recommendations

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Image 27
Contents Application Note Advanced Micro Devices, Inc. All rights reserved Contents Performance Guidelines for AMD Athlon 64 and AMD Opteron List of Figures List of FiguresList of Figures Revision History Revision HistoryRevision History Chapter Introduction IntroductionRelated Documents Chapter Introduction Introduction Experimental Setup Chapter Experimental SetupSystem Used Quartet Topology Internal Resources Associated with a Quartet Node Synthetic TestData Access Rate Qualifiers Axis Display Reading and Interpreting Test GraphsLabels Used Chapter Analysis and Recommendations Analysis and RecommendationsScheduling Threads Multiple Threads-Independent DataData Locality Considerations Multiple Threads-Shared DataScheduling on a Non-Idle System Hop Keeping Data Local by Virtue of first Touch Chapter Analysis and Recommendations Analysis and Recommendations Myth All Equal Hop Cases Take Equal Time Threads access local dataAvoid Cache Line Sharing Common Hop Myths DebunkedHop Hop Hop Myth Greater Hop Distance Always Means Slower Time 102% 108% 107% 147% 126% 125% 136% 145% 136% 127% 126% 146% 129% 139% Locks Performance Guidelines for AMD Athlon 64 and AMD Opteron Analysis and Recommendations Chapter Conclusions ConclusionsConclusions Appendix a Description of the Buffer QueuesAppendix a Appendix a What Role Do Buffers Play in the Throughput Observed? Performance Guidelines for AMD Athlon 64 and AMD Opteron Appendix a Controlling Process and Thread Affinity Support Under LinuxSupport under Microsoft Windows Support under SolarisMicrosoft Windows does not offer node interleaving Node Interleaving Configuration in the Bios CcNUMA Multiprocessor Systems Appendix a
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64 specifications

AMD64 is a 64-bit architecture developed by Advanced Micro Devices (AMD) as an extension of the x86 architecture. Introduced in the early 2000s, it aimed to offer enhanced performance and capabilities to powering modern computing systems. One of the main features of AMD64 is its ability to address a significantly larger amount of memory compared to its 32-bit predecessors. While the old x86 architecture was limited to 4 GB of RAM, AMD64 can theoretically support up to 16 exabytes of memory, making it ideal for applications requiring large datasets, such as scientific computing and complex simulations.

Another key characteristic of AMD64 is its support for backward compatibility. This means that it can run existing 32-bit applications seamlessly, allowing users to upgrade their hardware without losing access to their existing software libraries. This backward compatibility is achieved through a mode known as Compatibility Mode, enabling users to benefit from both newer 64-bit applications and older 32-bit applications.

AMD64 also incorporates several advanced technologies to optimize performance. One such technology is the support for multiple cores and simultaneous multithreading (SMT). This allows processors to handle multiple threads concurrently, improving overall performance, especially in multi-tasking and multi-threaded applications. With the rise of multi-core processors, AMD64 has gained traction in both consumer and enterprise markets, providing users with an efficient computing experience.

Additionally, AMD64 supports advanced vector extensions (AVX), which enhance the capability of processors to perform single instruction, multiple data (SIMD) operations. This is particularly beneficial for tasks such as video encoding, scientific simulations, and cryptography, allowing these processes to be executed much faster, thereby increasing overall throughput.

Security features are also integrated within AMD64 architecture. Technologies like AMD Secure Execution and Secure Memory Encryption help protect sensitive data and provide an enhanced security environment for virtualized systems.

In summary, AMD64 is a powerful and versatile architecture that extends the capabilities of x86, offering enhanced memory addressing, backward compatibility, multi-core processing, vector extensions, and robust security features. These innovations have positioned AMD as a strong competitor in the computing landscape, catering to the demands of modern users and applications. The continuous evolution of AMD64 technology demonstrates AMD's commitment to pushing the boundaries of computing performance and efficiency.