Pioneer PRO-610HD, PRO-510HD System micro-computer IC ∙ Pin Function, Pin Name Pin Function

PRO-610HD, PRO-510HD, SD-582HD5, SD-532HD5

PD3420A8 (SUB VIDEO SERVICE ASSY : IC3801) (PRO-610HD, PRO-510HD ONLY)

•I/P System micro-computer IC

∙Pin Function

No.	Pin Name	I/O		Pin Function	No.	Pin Name	I/O	Pin Function
1	VCC	−	Power supply (+5V)		51	A14	I
2	CS7	O			52	A15	I
3	CS6	O	Non connection		53	A16	O	Non connection
4	CS5	O			54	A17	O
5	CS4	O	Chip select of PE5066A		55	A18	O
6	UCAS	O	Data phase control of PE5067A		56	A19	O
7	LCAS	I/O	For microcomputer communication		57	VSS	−	Ground
8	PB6	O			58	WAIT	I	WAIT signal of PE5067A
			(Not used)
9	PB7	I			59	BREQ	I	Non connection
10	FEW	I	For writing the flash		60	BACK	O	Compulsory hardware through of PE5067A
								(Not used)
11	VSS	−	Ground		61	P18 (φ)	I	Clock output
12	P90	O	Error signal for communicating with main unit		62	STBY	I	−−
			microcomputer
13	TxD1	O	For writing the flash		63	RES	I	Hardware reset of I/P microcomputer
14	RxD0	I	Data for communicating with main unit		64	NMI	I	−−
			microcomputer
15	RxD1	I	For writing the flash		65	VSS	−	Ground
16	SCK0	I	Clock for communicating with main unit		66	EXTAL	I
			microcomputer
								Connect a crystal oscillator
17	P95	O	Busy for communicating with main unit		67	XTAL	I
			microcomputer
18	D0				68	VCC	−	Power supply (+5V)
19	D1	O	For test		69	AS	O	Non connection
20	D2				70	RD	O	RD for PE5066A/5067A
21	D3				71	HWR	O	HWR for PE5066A/5067A
22	VSS	−	Ground		72	LWR	O	−−
23	D4				73	MD0	I	−−
24	D5	O	For test		74	MD1	I	−−
25	D6				75	MD2	I	−−
26	D7				76	AVCC	−	Power supply (+5V)
27	D8				77	VREF	−	Reference voltage setting (+5V)
28	D9				78	P70	I
29	D10				79	P71	I
30	D11	I/O	Data bus 8-bit		80	P72	I	Non connection
31	D12				81	P73	I
32	D13				82	P74	I
33	D14				83	P75	I
34	D15				84	P76	I	PLL unlock detection (Not used)
35	VCC	−	Power supply (+5V)		85	P77	I	Obtain the external film information
								(Not used)
36	A0				86	AVSS	−	Ground
37	A1				87	IRQ0	I	Obtain the film information
38	A2				88	IRQ1	I	Obtain the histogram
39	A3	O	Address bus	12-bit	89	IRQ2	I	Vertical sync input
40	A4				90	IRQ3	O	Chip select of PE5067A
41	A5				91	CS0	I	Field judgement
42	A6				92	VSS	−	Ground
43	A7				93	PA0	I	System frequency detection (Not used)
44	VSS	−	Ground		94	PA1	I	Horizontal sync input
45	A8				95	PA2	O	−−
46	A9	O	Address bus	12-bit	96	PA3	O	−−
47	A10				97	PA4	O	For test
48	A11				98	PA5	O
49	A12	I	Non connection		99	PA6	O	IP process (PE5066A) stop control
50	A13	I	Non connection		100	PA7	O	IP system reset

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