Analog Devices HSC-ADC-EVALC warranty Features, Equipment Needed, Product Highlights

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High Speed Converter Evaluation Platform

FEATURES

Xilinx Virtex-4 FPGA-based buffer memory board Used for capturing digital data from high speed ADC evaluation boards to simplify evaluation

64 kB FIFO depth

Parallel input at 644 MSPS SDR and 800 MSPS DDR Supports 1.8 V, 2.5 V, and 3.3 V CMOS and LVDS interfaces Supports multiple ADC channels up to 18 bits Measures performance with VisualAnalog

Real-time FFT and time domain analysis Analyzes SNR, SINAD, SFDR, and harmonics

Simple USB port interface (2.0)

Supports ADCs with serial port interfaces (SPI)

FPGA reconfigurable via JTAG, on-board EPROM, or USB On-board regulator circuit speeds setup

5 V, 3 A switching power supply included Compatible with Windows 98 (2nd edition), Windows 2000,

Windows ME, and Windows XP

EQUIPMENT NEEDED

Analog signal source and antialiasing filter Low jitter clock source

High speed ADC evaluation board and ADC data sheet PC running Windows 98 (2nd edition), Windows 2000,

Windows ME, or Windows XP Latest version of VisualAnalog

USB 2.0 port recommended (USB 1.1 compatible)

HSC-ADC-EVALC

PRODUCT HIGHLIGHTS

1.Easy to Set Up. Connect the included power supply along with the CLK and AIN signal sources to the two evaluation boards. Then connect to the PC via the USB port and evaluate the performance instantly.

2.USB Port Connection to PC. PC interface is via a USB 2.0 connection (1.1 compatible) to the PC. A USB cable is provided in the kit.

3.64 kB FIFO. The on-board FPGA contains an integrated FIFO to store data captured from the ADC for subsequent processing.

4.Up to 644 MSPS SDR/800 MSPS DDR Encode Rates on Each Channel. Multichannel ADCs with encode rates up to 644 MSPS SDR and 800 MSPS DDR can be used with the ADC capture board.

5.Supports ADCs with Serial Port Interface or SPI. Some ADCs include a feature set that can be changed via the SPI. The ADC capture board supports these SPI-driven features through the existing USB connection to the computer without additional cabling needed.

6.VisualAnalog™. VisualAnalog supports the HSC-ADC- EVALC hardware platform as well as enabling virtual ADC evaluation using ADIsimADC™, Analog Devices proprietary behavioral modeling technology. This allows rapid compari- son between multiple ADCs, with or without hardware evaluation boards. For more information, see AN-737 at www.analog.com/VisualAnalog.

FUNCTIONAL BLOCK DIAGRAM

POWER

ON-BOARD

 

HSC-ADC-EVALC

 

 

 

 

USB

 

CONNECTOR

VOLTAGE

 

 

 

 

 

 

 

REGULATORS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SINGLE OR MULTICHANNEL

FPGA

 

LED2

LED1

UPLOAD

CAPTURE

 

HIGH SPEED ADC

 

 

CONFIGURATION

 

 

EVALUATION BOARD

 

MODE

 

DATA(16)

PORTB

 

 

 

 

 

 

DATA BUS 2(18)

 

 

 

FILTERED

 

n

J3*

 

PORTD

 

J6

 

 

FIFO

 

 

ANALOG

LOGIC

 

 

CLKA(2)

 

 

USB

 

 

INPUT

 

 

 

FPGA

CONTROL(9)

 

 

ADC

 

 

 

 

 

CONTROLLER

 

 

 

 

 

 

 

 

USB

 

n

 

DATA BUS 1(18)

 

 

 

PORTC

CONNECTOR

 

 

J2*

 

 

 

 

 

 

CLKB(2)

 

 

 

PORTE

 

STANDARD

 

 

 

 

 

 

 

 

 

 

 

 

EXT SYNC1

 

 

 

PORTA

 

CLOCK

 

 

 

FPGA

 

 

USB

 

USB 2.0

 

 

 

 

DONE

 

 

ONBOARD

 

CIRCUIT

 

 

 

EXT SYNC2

 

 

CONFIG

 

 

 

 

 

 

 

VOLTAGE

J4

 

 

 

 

 

 

 

PROM

 

 

 

 

 

 

 

 

FPGA

REGULATORS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CONFIG

POWER

 

 

 

 

FPGA GPIO(8)

 

 

 

PROM

CONNECTOR

 

SPI

 

J1*

SPI(7)

 

 

 

RECONFIG

 

 

 

 

USB DIRECT(5)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

J10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

*DATA CONVERTER I/O CONNECTORS

 

 

 

JTAG

 

 

 

 

 

 

 

 

 

 

CONNECTOR

 

CLOCK INPUT

Figure 1.

Rev. 0

06676-001

Evaluation boards are only intended for device evaluation and not for production purposes. Evaluation boards as supplied “as is” and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. No license is granted by implication or otherwise under any patents or other intellectual property by application or use of evaluation boards. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devicesforitsuse,norforanyinfringementsofpatentsorotherrightsofthirdpartiesthatmayresult from its use. Analog Devices reserves the right to change devices or specifications at any time without notice.Trademarks and registered trademarks are the property of their respective owners. Evaluationboardsarenotauthorizedtobeusedinlifesupportdevicesorsystems.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

©2007 Analog Devices, Inc. All rights reserved.

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Contents Functional Block Diagram FeaturesEquipment Needed Product HighlightsHSC-ADC-EVALC Table of Contents Product Description HSC-ADC-EVALCEvaluation Board Description Connection and Setup Power SuppliesHSC-ADC-EVALC ADC Capture Board Easy Start Jumpers U4 DIP Switch SettingJumper Number Description HSC-ADC-EVALC Components Top View HSC-ADC-EVALC ADC Capture Board FeaturesHSC-ADC-EVALC Components Bottom View HSC-ADC-EVALC Supported ADC Evaluation BoardsHSC-ADC-EVALC Theory of Operation HSC-ADC-EVALC Schematics HSC-ADC-EVALC Evaluation Board Schematics and ArtworkSram Address and Control Fpga to Sram Data AD19 to be Used with Higher Density Sram Devices Sram and Fpga Power Sram a Bypass CAP Unused Rocket I/0 Connections Rocket I/0 Connections USB Connections Rev Page 18 EZ-KIT Expansion Interface for DSPs Tyco HM Configuration Eeprom Power and Voltage Regulators Top Silkscreen PCB LayoutHSC-ADC-EVALC J1 HS-SERIAL/SPI/AUX Schematic Net Name Fpga Pin Connector J2HSC-ADC-EVALC J3 I/O Connections to Fpga U1 Connector J3Qty HSC-ADC-EVALC Ordering InformationManufacturer Part NumberR16 Qty Reference Designator DescriptionModel Description Ordering Guide ESD CautionRev Page 31 Rev Page 32