Analog Devices HSC-ADC-EVALC warranty PCB Layout, Top Silkscreen

Page 23

HSC-ADC-EVALC

PCB LAYOUT

GENERAL PURPOSE I/O,

USB/SPI CONTROL

XILINX

VIRTEX-4

FPGA

DEBUG

PINS

EXTERNAL

SYNC I/O

DATA BUS 1

DATA BUS 2

FPGA LOAD

SELECT

ON BOARD

POWER SUPPLY

100MHz

OSCILLATOR

FPGA I/O

VOLTAGE MODE

CYPRESS USB CONTROLLER

FPGA CONFIG PROM

06676-019

USB CONNECTOR	FPGA JTAG	5VDC POWER
	CONNECTOR	INPUT

Figure 19. Top Silkscreen

06676-020

Figure 20. Bottom Silkscreen

Rev. 0 Page 23 of 32

Image 23

Contents Product Highlights FeaturesFunctional Block Diagram Equipment NeededHSC-ADC-EVALC Table of Contents Evaluation Board Description HSC-ADC-EVALCProduct Description HSC-ADC-EVALC ADC Capture Board Easy Start Power SuppliesConnection and Setup Jumper Number Description U4 DIP Switch SettingJumpers HSC-ADC-EVALC Components Top View HSC-ADC-EVALC ADC Capture Board FeaturesHSC-ADC-EVALC Components Bottom View HSC-ADC-EVALC Supported ADC Evaluation BoardsHSC-ADC-EVALC Theory of Operation HSC-ADC-EVALC Schematics HSC-ADC-EVALC Evaluation Board Schematics and ArtworkSram Address and Control Fpga to Sram Data AD19 to be Used with Higher Density Sram Devices Sram and Fpga Power Sram a Bypass CAP Unused Rocket I/0 Connections Rocket I/0 Connections USB Connections Rev Page 18 EZ-KIT Expansion Interface for DSPs Tyco HM Configuration Eeprom Power and Voltage Regulators Top Silkscreen PCB LayoutHSC-ADC-EVALC J1 HS-SERIAL/SPI/AUX Schematic Net Name Fpga Pin Connector J2HSC-ADC-EVALC J3 I/O Connections to Fpga U1 Connector J3Part Number HSC-ADC-EVALC Ordering InformationQty ManufacturerR16 Qty Reference Designator DescriptionModel Description Ordering Guide ESD CautionRev Page 31 Rev Page 32