Analog Devices HSC-ADC-EVALC warranty Hsc-Adc-Evalc

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Rev.	Figure 21.
0 Page 24 of 32	J2 and J3 PinMapping

D	D
C	C
B	B
A	A

	I/O CONNECTOR—J1,	HSC-ADC-EVALC
	J2, AND J3 PIN
D	MAPPING
C
B
B
A

LVDS DATA PATH > CMOS/LVDS DATA PATH >

LVDS DATA PATH > CMOS/LVDS DATA PATH >

D17A–	D16A– D14A–		D12A–	D10A–		D8A–	D6A–	D4A–	D2A–	D0A–
D17A+	D16A+ D14A+		D12A+	D10A+		D8A+	D6A+	D4A+	D2A+	D0A+

DCLKA1–	D15A–	D13A–	D11A–		D9A–	D7A–	D5A–	D3A–	D1A–	DCLKA2–
DCLKA1+	D15A+	D13A+	D11A+		D9A+	D7A+	D5A+	D3A+	D1A+	DCLKA2+

(J3) DATA BUS 2

D17B–	D16B–	D14B–	D12B–	D10B–	D8B–	D6B–	D4B–	D2B–	D0B–
D17B+	D16B+	D14B+	D12B+	D10B+	D8B+	D6B+	D4B+	D2B+	D0B+

DCLKB1–	D15B–	D13B–	D11B–	D9B–	D7B–	D5B–	D3B–	D1B–	DCLKB2–
DCLKB1+	D15B+	D13B+	D11B+	D9B+	D7B+	D5B+	D3B+	D1B+	DCLKB2+	06676-021
			(J2) DATA BUS 1							06676-021

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Contents Features Functional Block DiagramEquipment Needed Product HighlightsHSC-ADC-EVALC Table of Contents HSC-ADC-EVALC Product DescriptionEvaluation Board Description Power Supplies Connection and SetupHSC-ADC-EVALC ADC Capture Board Easy Start U4 DIP Switch Setting JumpersJumper Number Description HSC-ADC-EVALC ADC Capture Board Features HSC-ADC-EVALC Components Top ViewHSC-ADC-EVALC Supported ADC Evaluation Boards HSC-ADC-EVALC Components Bottom ViewHSC-ADC-EVALC Theory of Operation HSC-ADC-EVALC Evaluation Board Schematics and Artwork HSC-ADC-EVALC SchematicsSram Address and Control Fpga to Sram Data AD19 to be Used with Higher Density Sram Devices Sram and Fpga Power Sram a Bypass CAP Unused Rocket I/0 Connections Rocket I/0 Connections USB Connections Rev Page 18 EZ-KIT Expansion Interface for DSPs Tyco HM Configuration Eeprom Power and Voltage Regulators PCB Layout Top SilkscreenHSC-ADC-EVALC J1 HS-SERIAL/SPI/AUX Connector J2 Schematic Net Name Fpga PinConnector J3 HSC-ADC-EVALC J3 I/O Connections to Fpga U1HSC-ADC-EVALC Ordering Information QtyManufacturer Part NumberQty Reference Designator Description R16Ordering Guide ESD Caution Model DescriptionRev Page 31 Rev Page 32