Analog Devices HSC-ADC-EVALC warranty J1 HS-SERIAL/SPI/AUX

Page 25

HSC-ADC-EVALC

HIGH SPEED SERIAL

REFERENCE CLK

HIGH SPEED SERIAL

DATA INPUTS

FUTURE HIGH SPEED SERIAL DATA INPUTS

FPGA GENERAL

PURPOSE I/O

SPI CONTROL (3.3V)

USB DIRECT I/O (3.3V)

D									D
C									C
B									B
A									A
MGTCLK1–	SD1–	SD2–	SD3–	SD4–	SD5–	SD6–	SD7–	SD8–	MGTCLK2–
MGTCLK1+	SD1+	SD2+	SD3+	SD4+	SD5+	SD6+	SD7+	SD8+	MGTCLK2+
I/O_1	I/O_3	I/O_5	I/O_7	SCLK	SDI	SDO	USB_1	USB_2	USB_4
I/O_2	I/O_4	I/O_6	I/O_8 CSB_1 CSB_2			CSB_3	CSB_4	USB_3	USB_5
			(J1) HS-SERIAL/SPI/AUX

06676-022

Figure 22. J1 Pin Mapping

13.843mm	38mm	32mm	43.155mm
1.4mm

J1

HS-SERIAL/SPI/AUX

J2

	J3
DATA BUS 1	DATA BUS 2

06676-023

Figure 23. Data Converter I/O Connector Placement (Top View)

Rev. 0 Page 25 of 32

Image 25

Contents Functional Block Diagram FeaturesEquipment Needed Product HighlightsHSC-ADC-EVALC Table of Contents Product Description HSC-ADC-EVALCEvaluation Board Description Connection and Setup Power SuppliesHSC-ADC-EVALC ADC Capture Board Easy Start Jumpers U4 DIP Switch SettingJumper Number Description HSC-ADC-EVALC Components Top View HSC-ADC-EVALC ADC Capture Board FeaturesHSC-ADC-EVALC Components Bottom View HSC-ADC-EVALC Supported ADC Evaluation BoardsHSC-ADC-EVALC Theory of Operation HSC-ADC-EVALC Schematics HSC-ADC-EVALC Evaluation Board Schematics and ArtworkSram Address and Control Fpga to Sram Data AD19 to be Used with Higher Density Sram Devices Sram and Fpga Power Sram a Bypass CAP Unused Rocket I/0 Connections Rocket I/0 Connections USB Connections Rev Page 18 EZ-KIT Expansion Interface for DSPs Tyco HM Configuration Eeprom Power and Voltage Regulators Top Silkscreen PCB LayoutHSC-ADC-EVALC J1 HS-SERIAL/SPI/AUX Schematic Net Name Fpga Pin Connector J2HSC-ADC-EVALC J3 I/O Connections to Fpga U1 Connector J3Qty HSC-ADC-EVALC Ordering InformationManufacturer Part NumberR16 Qty Reference Designator DescriptionModel Description Ordering Guide ESD CautionRev Page 31 Rev Page 32