ADC12V170 Evaluation Board User’s Guide
…, D11+/-) being emitted with one clock edge during the first half of the clock period and the other half of the data (even bits: D0+/-, D2+/-, …, D10+/-) being emitted with the opposite clock edge during the second half of the clock period. The odd data bits should be captured with the falling edge of DRDY and the rising edge of DRDY should be used to capture the even bits of the data.
The data is available on the evaluation board at pins A5/B5 (MSB +/-) through A10/B10 (LSB +/-) of the FutureBus connector (schematic reference designator FB). Please keep in mind that because the data is in DDR format, pins A5/B5 will carry data bit D11+/- during the first half of the clock period and these lines will carry bit D10+/- during the second half of the clock period. Similarly, pins A10/B10 will carry D1+/- during the first half of the clock period and these pins will carry D0+/- during the second half of the clock period. The
DRDY signal which is used to capture the data is also in LVDS format and it is available at pins A4/D4 (DRDY+/-) on the FutureBus connector. The over- range bit (OVR) LVDS signal is available on pins D22/D21 (OVR+/-) on the FutureBus connector.
Please see the Evaluation Board schematic in Section 5.0 and the ADC12V170 datasheet for further details.
4.5 Power requirements.
Power to the ADC12V170 evaluation board is supplied through the green power connector labeled “+5V” which is located along the bottom edge of the board. Voltage and current requirements are:
•+5V capable of providing up to 500mA (ADC12V170 evaluation board only)
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