ST92195B - GENERAL INFORMATION
Figure 1. ST92195 Block Diagram
NMI
INT[7:4]
INT2
INT0
OSCIN OSCOUT 
RESET
RESETO
SDO/SDI 
SCK 
Up to 64
Kbytes ROM
256bytes
RAM
Up to 8 |
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Kbytes | TRI | |
TDSRAM | ||
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256bytes
Register File
CPU
MMU
Interrupt
Management
ST9+ CORE
RCCU
TIMER/
WATCHDOG
SPI
MEMORY BUS |
REGISTER BUS
I/O | 8 | |
PORT 0 | ||
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I/O | 6 | |
PORT 2 | ||
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I/O | 4 | |
PORT 3 | ||
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I/O | 8 | |
PORT 4 | ||
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I/O | 2 | |
PORT 5 | ||
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DATA |
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SLICER |
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& ACQUI- |
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SITION |
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UNIT |
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SYNC.
EXTRAC- 
TION
VPS/WSS
DATA
SLICER
ADC
P0[7:0]
P2[5:0]
P3[7:4]
P4[7:0]
P5[1:0]
TXCF
CVBS1
WSCR1
WSCF1
CVBS2
AIN[4:1]
EXTRG
TIMING AND
MCFM 
CLOCK CTRL
SYNC |
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| VSYNC |
CONTROL |
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| HSYNC/CSYNC |
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| CSO | |
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STOUT |
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| STANDARD | |
| TIMER | |||
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| VOLTAGE | |
VSO[2:1] | ||||
SYNTHESIS | ||||
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ON
SCREEN
DISPLAY
PWM
D/A CON-
VERTER
FREQ.
PXFM
MULTIP.
R/G/B/FB
TSLU
HT
PWM[7:0]
1Not available on all devices.
All alternate functions (Italic characters) are mapped on Ports 0, 2, 3, 4 and 5
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