EN 80 |
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| DVD963SA | Circuit Descriptions and List of Abbreviations |
Input
Input data comes from the
Signal Processing
For video, the input data stream is decoded to the appropriate MPEG, Sub Picture, and OSD data streams, after which they
Block diagram
To Host processor
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| Host interface |
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HF |
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| interface |
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From Host processor (STi 55XX)
PCM IEC 958
PCM_CLK
DSD_CLK
are fed to the PAL/NTSC encoder. This cell will convert the digital MPEG/Sub Picture/OSD stream into a standard base band signal and into RGB components. It handles interlaced and
For audio, the processing cell is a fully compatible DTS, Dolby Digital
(BE Interface)
I2S
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| Decryption |
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| Processor |
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| Demux |
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| SACD |
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| SDRAM |
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IEC 958
gen.
DSD
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| mix |
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decoder |
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IEC 958
I2S
PCM
DSD/PCM
MUTE
Output
For video, six analogue output pins are available on which CVBS,
to 16 Mbit/64 Mbit | AUD_CLK | SYS_CLK |
SDRAM | 256/384/512/718*FS | |
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CL 26532053_021.eps 260402
via a buffer, to connector 1703. As an option, a digital YUV output is available at connector 1704.
External Memory
The STi55xx family is capable of accessing external memory via three buses:
•The enhanced memory interface (EMI). This interface is configurable and can be used to access Flash, ROM, and various flavours of DRAM.
•The shared memory interface (SMI). The SMI is only used to access SDRAM. The SMI is connected to a 64Mbits (4M x 16bit) 7.5ns SDRAM (item 7500). The SDRAM has the following functions:
–It is used by the MPEG video decoder as a frame buffer,
–It holds the software and the variables used by it.
•The I2C bus. Via this bus, the NVRAM (or EEPROM) is accessible. This memory is used to store user settings, player settings, and region code. As the STi55xx
5V | 3V3 |
3k3 3k3 (optional)
5V I2C levels | 3.3V I2C levels |
CL 16532163_050.eps 230102
Figure 9-5 I2C voltage level shifter
The SACD DSD processor
The
The
During SACD application, the STi55xx serves as a host, whereby the Furore is controlled via the EMI interface. The Furore processing part is not used during all other play modes. In these modes, the PCM audio signals are fed through the Furore to the appropriate DAC.
Figure 9-6 Block diagram Furore
We can divide the
1.Host interface. This is the link between the host bus and the internal registers and memory bus. It also supplies the general reset signal (HW and SW) and the interrupt signals.
2.Data processing. All modules and peripherals in this part are connected to a
3.Copy protection. On every SACD disc, a
4.DSD decoding and post processing. In this part, all processing is done to generate a DSD and/or an I2S stream (from the
Interfaces
•Basic Engine Interface:
–Data input interface. The Basic Engine Interface (I2S) is connected to the output of the SAA7335 (HD61) high speed CD decoder.
–Analogue HF input. The analogue HF input, coming from the optical pickup unit (OPU), is also fed to the
•SDRAM Interface: The SDRAM interface forms a glue less interface to one 64 Mbit SDRAM device. The interface takes care for the
•Audio data input/output Interface:
–DSD/PCM combined data output. DSD_PCM: Output intended for a combined
–Stereo DSD only output. DSD_stereo: