i.Pulse Width: in number of clocks
ii.Output polarity: Low or High true
iii.Strobe#l wire: Output the HDrive signal to strobe1 and strobe1 ++1 wires in addition to the HDrive wire
iv.Clocks from Data to Hsync: number of clocks from last pixel on the line to following horizontal sync.
v.For cameras that use Vertical Drive, the frame grabber generates a V drive pulse and the camera synchronizes to it. The camera then generates an FDV (Frame Data Valid) signal and sends it back to the frame grabber. The frame grabber uses the FDV to detect the starting line of each frame from the camera.
•Pulse Width: in number of clocks
•Output polarity: Low or High true
•Strobe#O wire: Output the VDrive signal to strobe#O and strobe#O++l wires in addition to the VDrive wire
•Clocks from Data to V sync: number of lines from last line to fol- lowing vertical sync.
b)If your camera is an interlaced camera, enter the appropriate information under Interlace Control.
•Starting Field: either O or 1
•First Line Length: Length of the first line on field 0 and field 1. Both fields are usually set to the width of the image size.
•Vdrive offset: Number of pixel clocks after the edge of the Hdrive that
•Vdrive goes active.
c)If your camera requires a clock from the PXDl000 set the Clocks per Pixel. Most cameras require one clock per pixel, but some require two. Refer to your camera manual for the correct setting.
d)Set the Strobe/Drive Signal. This is the type of output signals generated by the frame grabber (either RS422 or TTL), for HDrive, VDrive, strobeO, and strobel.
Relationship to various pins
Camera Control 0,1,2 general purpose control pins can be used to control camera modes. For example the Dalsa
Troubleshooting tips and hints when using the PXD Configuration Application.
Shape edges or ring around the images:
Shape edges or rings around the image on the screen may indicate that the pixel clock lines need to be swapped. Swap the lines in the cable to the pixel clock
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