Sanyo EP92H New Charge Pump ICs, LV5711FN, White LED, CCD Power Supply IC for Camera Cell Phones

Support for High-Resolution CCDs

New Charge Pump ICs

Features of New Charge Pump ICs

CCD image sensors require a high drive voltage of 10 to 20 V. This 10 to 20 V level is created by stepping up the 3 V power supply level.

Since conventional charge pump voltage step-up technologies suffer from increased power loss when used to step up the original voltage by over three times, their use in cell phones was problematic.

SANYO has, however, discovered a way of fusing their high level analog circuit and device technologies to overcome this problem.

This new charge pump technology can step up a regulated voltage by a factor of three or higher with an efficiency as high as 70%. Furthermore it can provide an output current of several tens of mA.

SANYO was the first in the industry to develop a high-performance charge pump.

This new charge pump technology can provide both positive and negative stepped up levels, can be combined into multiple stages, and can provide multiple output levels. Thus this circuit technology is optimal for use in future camera cell phones that include a megapixel-class CCD image sensor.

This IC is based on a unique SANYO idea and is a high-efficiency charge pump IC that was newly-developed taking advantage of CMOS technologies that fuse SANYO's circuit and process technologies. This IC is optimal for power supplies in portable electronic equipment.

This IC introduces technologies that completely overturn the previous common knowledge that although charge pump circuits were low noise, they suffered from poor efficiency.

Charge pump power supply application

The ability to provide a stepped-up voltage with low noise makes this circuit optimal for embedding in modules.

		+15 V(10 mA)	CCD
3 V	Charge pump
		-8 V(5 mA)
		+7 V(500 ∝A)
3 V	Charge pump		LTPS
		-8 V(5 mA)
3V	Charge pump	+4.5 V(100 mA)	White LED

CCD Power Supply IC for Camera Cell Phones

●High efficiency

(Prior to the regulator: 90 to 95 %)

●Coilless, low noise

●Supports high output current designs

●The only external components are thin form capacitors (no coils or diodes required)

●Can provide both positive and negative stepped-up outputs

●Supports fine step-up step sizes

+0.5 ⋅ n ⋅ VDD

-0.5 ⋅ n ⋅ VDD (n: integer)

●Optimal for use as the power supply in portable equipment

IPBlock diagram

Clock Clock generator & driver

C1	C2	Cn	Cn+1
VDD
VIN	Charge pump	VOUT	Regulator	VO

LV5711FN

●Regulates a 3.3 to 4.5 V battery level to 3.1 V and steps up that level 3⋅ and 6⋅ using a charge pump, to provide the two regulated power supply levels required by the CCD image sensor.

●VH = +15.0 V

●VL = -8 V

●Two independent charge pump systems are provided for VH and VL

●Built-in regulators for the analog system power supply, vertical driver system, and DSP core

Under

development

Block diagram

3.3 to 4.5 V

VBAT2

VBAT1

4

∝

8

1

F

OUT2

VSS1

7

6

1 ∝F

VBAT3

3.1 V / 100 mA

3.1 V / 100 mA

OUT1

1 ∝F

10

LDO

LDO

5

VBAT4	13			VDD1,2,3,4
OUT3			39	VDD1
	11	3.1 V / 1 mA
1 ∝F			32	VDD2
VSS2
	9
OUT4	12	1.8 V / 100 mA	40	C11A	0.22 ∝F
1∝F		LDO			(VDD✕1)
FVREF	26		38	C11B

Sample characteristics of a high-current charge pump (single supply voltage→±3⋅)

Output voltages from positive and negative step-up operation

0.1 ∝F
VDD3	17	41		0.22 ∝F
			C12A	(VDD✕2)
	19	37
			C12B

Dependency of efficiency on the supply voltage

	90
	80
(%)	70
	60
Efficiency		3.5 V
	50	2.9 V
		3.1 V
	40	3.3 V
	30	3.7 V

20VDD=3.3V

At IOUT=50 mA, efficiency=80.6%

10At IOUT=100 mA, efficiency=72.0% Maximum efficiency: 80.8%

00 10 20 30 40 50 60 70 80 90 100

Output current, IOUT (mA)

■Plus step-up

Positive step-up voltage vs. output current

12

10 3.7 V

(V)								3.3 V
VOUT	8						2.9 V
voltage,
	6
Output	4
	2				IOUT=-50 mA
					At VDD=2.9 V, VPP=7.78 V
					At VDD=3.3 V, VPP=9.03 V
	0				At VDD=3.7 V, VPP=10.26 V
	0	10	20	30	40	50	60	70	80	90	100

Output current, IOUT (mA)

■Minus step-up

Negative step-up voltage vs. output current

-12

-10					2.9 V			3.7 V
(V)OUT	-8						3.3 V
V
voltage,	-6
Output	-4
	-2				IOUT=50 mA
					At VDD=2.9 V, Vbb=-7.44 V
					At VDD=3.3 V, Vbb=-8.71 V
	-0				At VDD=3.7 V, Vbb=-9.96 V
	0	10	20	30	40	50	60	70	80	90	100

Output current, IOUT (mA)

VSS4

6 times

15

42

0.22 ∝F

VSS5

C13A

Bandgap

step up

0.47 ∝F

20

circuit

36

(VDD✕3)

voltage

C13B

C21A

reference

1.19 V

43

0.22 ∝F

(VDD✕1)

18

C21B

C14A

(VDD✕4)

-3 times

35

0.47 ∝F

21

C14B

C22A

step up

16

circuit

44

0.22 ∝F

(VDD✕2)

C22B

C15A

(VDD✕5)

0.47 ∝F

34

22

C15B

C23A

Timing

33

generator

(VDD✕3)

14

VSS3

C23B

3

VL_C24

VSS6

23

(VDD✕3)

VH_C16

1 ∝F

1

Sequence

(VDD✕6)

VL_C25

24

-8-V Reg

generator

1 ∝F

1 ∝F

15-V Reg

2

VH_C17

STBY

30

1 ∝F

SLEEP

29

1.2-MHz

1/2 Divider

27

NC

Oscillator

31

28

25

EN

VDD4

VSS7

* Values in parentheses are actual

Note: Short OUT1 to VDD1 through VDD4.

applied voltages to the capacitor.

28 29