Motorola IC-T81A PLL Circuits, Power Supply Circuits Voltage Line, Line Description, Vcc, +3CPU

The APC sensor (R911) detects driving current from the drive voltage at the YGR (Q138), drive (Q921) and power (Q922) amplifiers. The detected current is converted into DC voltage at Q913, then applied to the APC control circuit (IC901, pin 2). The applied voltage is compared with a “PSET” voltage from the CPU via the D/A converter (LOGIC unit; IC5), and the APC control circuit outputs “VGGC” volt- age from pin 1 to control the YGR, drive and power ampli- fiers.

When the driving current is increased, input voltage of the differential amplifier (IC901, pin 2) will be increased. In such cases, the differential amplifier output voltage (IC901, pin 1) is decreased to reduce the driving current.

4-3 PLL CIRCUITS

4-3-1 50 MHz BAND PLL CIRCUIT (RF UNIT)

The osillated signal at the 6MVCO (Q341, D341) is amplified at the buffer amplifiers (Q342, Q343). The amplified signal is applied to the PLL IC (IC801, pin 2) via the buffer-amplifier (Q813).

The signal which is applied to the PLL IC (IC801) is divided by N-data from the CPU and phase-detected with the divid- ed reference frequency (5 kHz) then output from pin 8. The output signal is converted into DC voltage at the active filter (Q804, Q805) and is fed back to the 6MVCO as the lock volt- age.

4-3-2 144 MHz BAND PLL CIRCUIT (VCO BOARD AND RF UNIT)

The osillated signal at the 144-VCO circuit (VCO unit; Q311, Q312, D302 and D311) is amplified at the buffer amplifiers (VCO unit; Q313).The amplified signal is applied to the PLL IC (IC801, pin 19) via a buffer-amplifier (Q807).

The applied signal is divided by serial data from the CPU (N- data) and phase-detected with the divided reference fre- quency (5 kHz) at the phase detector section in the PLL IC. The phase-detected signal is output from IC801 (pin 13) and converted DC voltage at the active filter (Q811, Q812). The converted DC voltage is fed back to the VCO board as the “VLV” signal of the lock voltage.

While operating in the 144 MHz band, the lock voltage is applied to the CPU (LOGIC unit; IC1) via the tune control cir- cuit (Q803) to track the center frequency of the tunable bandpass filters (D306, D309, D310) as the “TUNE” signal.

4-3-3 440 MHz BAND PLL CIRCUIT (VCO BOARD AND RF UNIT)

The osillated signal at the 440-VCO circuit (VCO unit; Q321, Q322, D321 and Q322) is amplified at the buffer-amplifiers (VCO unit; Q323).The amplified signal is applied to the PLL IC (IC801, pin 19) via a buffer-amplifier (Q807).

The applied signal is divided by serial data from the CPU (N- data) and phase-detected with the divided reference fre- quency (5 kHz) at the phase detector section in the PLL IC. The phase-detected signal is output from IC801 (pin 13) and converted DC voltage at the active filter (Q811, Q812). The converted DC voltage is fed back to the VCO board as the “VLV” signal of the lock voltage.

4-3-4 1200MHz BAND PLL CIRCUIT (VCO BOARD AND RF UNIT)

The osillated signal at the 1200-VCO circuit (VCO unit; Q350, D351 and D352) is amplified at the buffer-amplifiers (VCO unit; Q351 and Q353). The signal passes through the buffer amplifier (Q354), the high-pass (C376–C380, L334 and L335) and the low-pass filter (C381–C385, L336 and L337). The filtered signal is applied to the PLL IC (IC802, pin 1) via the buffer amplifier (Q816).

The applied signal is divided by serial data from the CPU (N- data) and phase-detected with the divided reference fre- quency (5 kHz) at the phase detector section in the PLL IC. The phase-detected signal is output from IC801 (pin 13) and converted DC voltage at the active filter (Q811, Q812). The converted DC voltage is fed back to the VCO board as the “VLV” signal of the lock voltage.

4-4 POWER SUPPLY CIRCUITS VOLTAGE LINE

LINE	DESCRIPTION
HV	The voltage from the external power supply or
	attached battery pack.
	The same voltage as the “HV” line (external
VCC	power supply or battery pack) passed through a
	diode (RF unit; D1).
	Common 3V converted from the “VCC” line by
+3CPU	+3C CPU regulator IC (LOGIC unit; IC141). The
	output voltage is supplied to the +3C regulator
	circuits, etc.
	Common 3V converted from the “VCC” line by
+3C	the +3C regulator circuit (LOGIC unit; Q142 and
	Q145) using the +3CPU regulator (LOGIC unit;
	IC141.)
	Common 3V converted from the “VCC” line by
+3	the +3 regulator circuit (LOGIC unit; IC5, Q1, Q2
	and Q3) using the +3C regulator (LOGIC unit;
	Q142 and Q145).
	3V for receiver circuit converted from the “VCC”
R+3	line by the “R+3” regulator circuit (RF unit; Q7
	and Q8).
	4V for transmitter circuit converted from the
	“VCC” line by the T4 regulator circuit (RF unit;
T4	Q901–Q903 and D901). The T4 regulator circuit
	is controlled by the CPU (LOGIC unit; IC1, pin
	21) via the “TXC” line.

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