HP Vectra VL 5/xxx 5 manual PCI Bus Interface, Data Path, Controller

2 System Board

Chip-Set

PCI Bus Interface	Sequential PL-to-PCI memory write cycles are translated into PCI zero wait
	state burst cycles. The maximum PCI burst transfer can be from 256 bytes to
	4 KB. The chip supports advanced snooping for PCI master bursting, and
	provides a pre-fetch mechanism dedicated for IDE read.
	The PCI arbiter supports PCI bus arbitration for up to four masters using a
	rotating priority mechanism. Its hidden arbitration scheme minimizes
	arbitration overhead.
Data Path	Storage elements are provided for bidirectional data buffering among the 64-
	bit PL data bus, the 64/32-bit memory data bus, and the 32-bit PCI address/
	data bus.
	There are three FIFO (first-in first-out) queues, and one read buffer for the
	bridges of the PL, PCI, and Memory buses. This buffering is used, partly, to
	smooth the differences in bandwidths between the three buses, thereby
	improving the overall system performance. During bus operations between
	the PL, PCI and Memory buses, the chip receives control signals from the
	TXC, performs functions such as latching data, forwarding data to
	destination bus, data assemble and disassemble.
	Error correcting code (ECC) and parity bits are generated for memory
	writes, and optional parity checking for memory reads. This operation
	always sustains zero wait performance on PL-to-Memory, and always
	streams zero wait performance on PCI-to-Memory and Memory-to-PCI.
	Whilst accesses to the local memory are in progress, whether it be from the
	PL or PCI bus, the TXC maintains control of the secondary cache, DRAMs,
	and the datapath.
Level-2 Cache Memory	This unit controls the L2 cache memory, adopting a write back policy, in a
Controller	direct mapped organization. An 8-bit tag is used to allow the lowermost
	64 MB of main memory to be cached (if more than 64 MB of main memory is
	installed, accesses to the uppermost regions will be made directly to the main
	memory modules, and not via the cache memory mechanism). When a
	512 KB cache memory module is installed, the chip set allows provision for
	an 11-bit tag to be used to allow 512 MB of main memory to be cached, but
	this facility has not been enabled in the HP BIOS. More details on the use of
	HP cache memory are given on page 32.
	The cache memory line width is 32-bytes (256-bits), four times the width of
	the Processor-Local data bus. Reads and writes always involve a full cache
	line, and so require four back-to-back cycles on the bus. Since they involve

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