System Board Chip-Set | HP Vectra VL 5/xxx 5 guide

2 System Board

Chip-Set

accesses to related addresses, they do not need four independent accesses to main memory, but can be organized as a pipelined burst. The second, third and fourth cycles in each burst require less time to complete than the first. This is because the first cycle includes the addressing phase and memory pre-charge timing. The read and write access timing has the pattern 3-1-1-1. However, the timing for 64-byte burst reads can be even better than this (3-1-1-1,2-1-1-1 for a dual bank back-to-back burst read1, and 3-1-1-1,1-1-1-1 for a single bank back-to-back burst read2) provided that the main memory banks have been filled contiguously.

There are two programmable non-cacheable regions, with an option to disable local memory in these regions. A 64 KB to 1 MB cache summary is provided.

Main Memory Controller The main memory controller supports up to 512 MB of main memory (dynamic random access memory, DRAM), arranged in banks of any mixture of memory capacities, provided that each bank contains a pair of identical single interline memory modules (SIMMs). The HP Vectra VL 5/

xxxSeries 5 and XA 5/xxx PCs have provision for three banks. With the 32 MB module from HP, this gives a total capacity of 192 MB. With a future 64 MB module from HP, it will give a total capacity of 384 MB.

In the case of 66 MHz PL bus operation, memory accesses have a timing pattern of 5-2-2-2 for a page-hit. This degrades to 8-2-2-2 for a row-miss, and to 11-2-2-2 for a page-miss. When the banks have been filled in an arbitrary order, back-to-back burst reads keep to the 5-2-2-2,5-2-2-2 timing pattern. When the banks have been filled contiguously (bank A, then bank B, then bank C), back-to-back burst reads are improved to a 5-2-2-2,3-2-2-2 timing pattern.

The controller supports relocation of system management memory. It supports a read cycle power saving mode, and a CAS before RAS Intelligent Refresh mode of operation, with a CAS# driving current that is programmable.

The controller is fully configurable for the characteristics of the shadow RAM (640 KB to 1 MB). It supports concurrent write back. To implement the optional error correcting code (ECC) or parity checking, 36-bit SIMMs must be installed exclusively (see page 33 for more details).

1.As used for the HP 512 KB cache memory module.

2.As used for the HP 256 KB cache memory module.