Sony PCV-R532DS manual Uswc

80

VAIO Computer Reference Manual

Chip Configuration Sub-Menu
SDRAM Configuration	[By SPD]
	User Define
	7ns (143MHz)
	8ns (125MHz)
SDRAM CAS Latency	[2T]
SDRAM RAS to CAS Delay	[2T]
SDRAM RAS Precharge Time	[2T]
SDRAM Cycle Time (Tras, Trc)	[5T, 7T]
	6T, 8T
SDRAM Address Setup Time	[1T Delay]
	No Delay
SDRAM Page Closing Policy	[All Banks]
	One Bank
CPU Latency Timer	[Enabled]
	Disabled
Onboard VGA	[Enabled]
	Disabled
Display Cache Paging Mode	[Page Open]
	Page Close
Video Memory Cache Mode	[UC]
	USWC
Memory Hole At 15M-16M	[Disabled]
	Enabled
PCI 2.1 Support	[Enabled]
	Disabled
High Priority PCI Mode	[Enabled]
	Disabled
Onboard PCI IDE Enable	[Both]
	Primary
	Secondary
	Disabled