Analog Devices AD9843A manual Pin Number Name Type Description, PIN Configuration

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AD9843A

PIN CONFIGURATION

SCK

SDATA

SL

NC

STBY

NC

THREE-STATE DVSS

DVDD2

VRB

VRT

CML

DRVSS 1

DRVSS 2

(LSB) D0 3 D1 4 D2 5 D3 6

D4 7

D5 8

D6 9

D7 10

D8 11 (MSB) D9 12

NC = NO CONNECT

48 47 46 45 44 43 42 41 4039 38 37

PIN 1

IDENTIFIER

AD9843A

TOP VIEW

(Not to Scale)

13

14

15

16

17

18

19

20

21

22

23

24

DRVDD

DRVSS

DVSS

DATACLK

DVDD1

DVSS

PBLK

CLPOB

SHP

SHD

CLPDM

DVSS

36AUX1IN

35AVSS

34AUX2IN

33AVDD2

32BYP4

31NC

30CCDIN

29BYP2

28BYP1

27AVDD1

26AVSS

25AVSS

PIN FUNCTION DESCRIPTIONS

Pin Number

Name

Type

Description

 

 

 

 

1, 2

DRVSS

P

Digital Driver Ground

3–12

D0–D9

DO

Digital Data Outputs

13

DRVDD

P

Digital Output Driver Supply

14

DRVSS

P

Digital Output Driver Ground

15, 18, 24, 41

DVSS

P

Digital Ground

16

DATACLK

DI

Digital Data Output Latch Clock

17

DVDD1

P

Digital Supply

19

PBLK

DI

Preblanking Clock Input

20

CLPOB

DI

Black Level Clamp Clock Input

21

SHP

DI

CDS Sampling Clock for CCD’s Reference Level

22

SHD

DI

CDS Sampling Clock for CCD’s Data Level

23

CLPDM

DI

Input Clamp Clock Input

25, 26, 35

AVSS

P

Analog Ground

27

AVDD1

P

Analog Supply

28

BYP1

AO

Internal Bias Level. Decoupling

29

BYP2

AO

Internal Bias Level Decoupling

30

CCDIN

AI

Analog Input for CCD Signal

31

NC

NC

Leave Floating or Decouple to Ground with 0.1 μF

32

BYP4

AO

Internal Bias Level Decoupling

33

AVDD2

P

Analog Supply

34

AUX2IN

AI

Analog Input

36

AUX1IN

AI

Analog Input

37

CML

AO

Internal Bias Level Decoupling

38

VRT

AO

A/D Converter Top Reference Voltage Decoupling

39

VRB

AO

A/D Converter Bottom Reference Voltage Decoupling

40

DVDD2

P

Digital Supply

42

THREE-STATE

DI

Digital Output Disable. Active High

43

NC

NC

May be tied High or Low. Should not be left floating.

44

STBY

DI

Standby Mode, Active High. Same as Serial Interface Standby Mode

45

NC

NC

Internally Not Connected. May be Tied High or Low

46

SL

DI

Serial Digital Interface Load Pulse

47

SDATA

DI

Serial Digital Interface Data

48

SCK

DI

Serial Digital Interface Clock

 

 

 

 

TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.

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Image 6
Contents Functional Block Diagram Product DescriptionParameter Symbol Min Typ Max Unit Parameter Min Typ Max UnitAD9843A Power Consumption Maximum Clock Rate Temperature Package Model Range Description Option 20C to +85C Thin Plastic ST-48 Quad FlatpackThermal Resistance PIN Configuration Pin Number Name Type DescriptionPIN Function Descriptions Differential Nonlinearity DNL Power Supply Rejection PSRInternal Delay for SHP/SHD Peak NonlinearityAD9843A-Typical Performance Characteristics CCD-MODE and AUX-MODE Timing TIDRegister Address Data Bits Name D10 Serial Interface Timing and Internal Register DescriptionMSB LSB Dataclk CLP/PBLK SHP/SHDCCD-Mode Block Diagram Circuit Description and OperationCode Range Gain Equation dB MSB LSB D10 Gain dBRecommended Circuit Configuration for CCD-Mode Applications InformationOutline Dimensions Lead Lqfp ST-48

AD9843A specifications

The Analog Devices AD9843A is a high-performance, integrated analog-to-digital converter (ADC) designed for a variety of applications requiring precise signal conversion. This device boasts a 12-bit resolution, making it suitable for capturing fine details in complex signals. The AD9843A operates with a maximum sampling rate of up to 130 MSPS (mega samples per second), which allows it to handle fast-changing waveforms effectively, ideal for applications in the fields of telecommunications, instrumentation, and medical imaging.

One of the standout features of the AD9843A is its dual-channel architecture, which enables simultaneous sampling of two input signals. This capability is particularly beneficial in applications such as radar and sonar systems, where capturing multiple input sources in parallel is critical. Furthermore, the ADC incorporates a high-speed programmable gain amplifier (PGA), providing adjustable gain settings to accommodate a wide range of signal amplitudes, ensuring optimal performance across various input conditions.

The AD9843A employs Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) specifications, both of which contribute to its impressive accuracy and linearity. With a DNL of ±0.5 LSB (least significant bit) and an INL of ±1 LSB, the AD9843A minimizes distortion and enhances the fidelity of the digital representation of analog signals. Additionally, the device features low noise performance, which is essential for obtaining high-quality signal digitization, especially in sensitive applications where signal integrity is paramount.

Another key characteristic is the integrated sample-and-hold circuit that allows the ADC to capture input signals with minimal distortion during the conversion process. This design choice helps to stabilize the input signal, reducing the effect of sampling jitter. The AD9843A also provides various output data formats, including binary, gray code, and two's complement, which gives designers the flexibility to interface the ADC with different digital systems.

In terms of power consumption, the AD9843A is efficient, operating at a typical supply voltage of 5V. It offers a significant advantage for battery-operated devices by ensuring that the power requirements are kept low without compromising performance. With its combination of high throughput, low noise, and versatility, the Analog Devices AD9843A stands out as a robust solution for high-speed data acquisition systems, making it a preferred choice among engineers and designers across various industries.