Direct Digital Synthesis (DDS) Circuit Diagram
The phase accumulator is a standard |
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| 31 |
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really the heart of the DDS as it is the most significant bit of the accumulator that produces the |
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| divider[31:0] | 30 |
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variable frequency being synthesized. The remaining circuits only multiply, divide and clean this |
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synthesized frequency or are involved with selecting and generating the DDS control words. |
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The frequency of the most significant bit is defined by the |
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accumulator. This value is shown as ‘N’ on the LCD display and is applied to the bus |
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| frequency_ | 2 |
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‘dds_control_word’ in the circuit. The value of N is computed in such a way that the synthesized | freq_scaling | 1 |
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frequency is nominally in the range 6.25MHz to 12.5MHz so that it is always a suitable |
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input to the second DCM. |
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| to divide the low jitter clock by | |||
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| Counter | dds_scaling_word | powers of 2 and a multiplexer | ||||
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| N × 200MHz |
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| selects the appropriate course | ||||
FMSB = |
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| D | ||||
232 |
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| division factor. | ||||
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| synth_clk |
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In this example N=204010946 decimal so the output from the phase accumulator |
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| N × 200MHz × 16 | ||||
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| FO = | |||||
is ~9.5MHz (a period of approximately 105ns). That means that the accumulator |
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| 2(D+1) × 232 | ||||
synthesizes one output cycle for approximately 21 cycles of the 200MHz clock | frequency_aligned_dcm |
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from which the accumulator runs. |
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| DCM |
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| phase_accumulator[31:0] |
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| In the example, D=4 so the | |||
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phase_acc |
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| CLKIN | CLKFX | dcm_clean_clk | ~153MHz from the DCM is | ||||
N dds_control_word[31:0] | + |
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| CLKFX_MULTIPLY=256 |
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| BUFG | divided by 2(4+1)=32 | |||
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| FO=4.7499999869MHz | |||||||
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| CLKFX_DIVIDE=16 |
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| phase_acc_dcm |
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| The second DCM is used in a ‘frequency aligned mode’. At the time of writing this | |||||||
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50MHz |
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| 200MHz |
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| reference design, this mode is not an officially documented or supported feature. | ||||||
| DCM |
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| However, it is hoped that this reference design will enable you to see this mode in action | ||||||
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clk | CLKIN | CLKFX | clk_200mhz | dds_clk |
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| and evaluate it for yourself. In this mode, the DCM not only multiplies the input clock, but | ||||||
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BUFG | CLKFX_MULTIPLY=4 | BUFG |
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| also has the effect of reducing cycle to cycle jitter. This is because the normal phase | |||||||
| CLKFX_DIVIDE=1 |
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| alignment mode of the DCM has been disabled and the DCM is tracking the average of | |||||||
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| the input frequency instead. | In the example, the input to the DCM will have 5ns | ||||
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The first DCM is used to multiply the 50MHz clock by a |
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| of cycle to cycle jitter as the square wave is formed | ||||||
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factor or 4 and form a 200MHz clock. This gives the |
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| from 21 cycles of 200MHz. The DCM will generate | ||||||
phase accumulator a timing resolution of 5ns. |
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| 10 or 11 | 10 or 11 | ~153MHz square wave with <300ps of jitter. | |||||||
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| cycles | cycles |
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Frequency Generator for the