CDM V AM1250
Trig enta
HF amp.
Diode signals
Radial, focus
Motor, sledge
Loader assy
PROCESSOR DSA
CD10
SERVO
DECODER
IIS, DOBM
UDA1320 | ANA OUT | |
DAC | ||
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CL96532086_048.eps 080999
Connect on pin 2 of position 1208 a clock signal of 8.4672 MHz ( 100ppm minimum rise time of 50ns and at TTL level (0V and +5V).
Keep microprocessor 7202 in reset by forcing pin 7 at position 1208 to +5V.
Release the reset. Now, the processor will reset the CD10 for at least 75 µs.
The output clock CL11 should be available now at pin 42 of the CD10.
Check the following frequencies :
Figure
8.3.1 Supply Voltages |
Description |
The CD main board receives +5V and +12V from the CDR main |
board via respectively pin 16 and pin 15 of connector 1208. The |
+5V is split up into +5VHF and +5V. The +5VHF is used mainly |
Point
Position 7000 pin 16
Position 7202 pins 14,15
Position 7309 pin 6
Position 7309 pin 1
Position 7309 pin2
Frequency
8.4672 MHz ±100ppm
12MHz ±5%
11.2896 MHz ±100ppm
2.1168 MHz ±100ppm
44.1kHz ±100ppm
CL96532086_050.eps 080999
for the diode currents and the |
the digital part of the board. On the board a +3V3 is made from |
the +5V for the decoder CD10 and an A3V3 for the DAC |
UDA1320. The +12V is split up into A12V for the audio output |
stage and +12V for the power drivers of the CDM. |
Measurements
Connect following supplies to next pins :
+5V + 5% to pin 16 of connector 1208.
+12V + 5% to pin 15 of connector 1208. Ground reference to pin 17 of connector 1208.
Figure
8.3.3CD10 Decoder/Servo SAA7324 (7000)
Description
The CD10 is a single chip combining the functions of a CD decoder, digital servo and bitstream DAC. The decoder/servo part is based on the CD7. The decoding part supports a full audio specification and can operate at single speed (n=1) and double speed (n=2).
Block Diagram
| Keep microprocessor 7202 in reset by forcing pin 7 of |
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| VSSA2 | VDDA2 | VSSD2 |
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| D1 | D2 | D3 | D4 | VSSA1 | VDDA1 | VSSD1 | VSSD3 | VDDD1(P) | VDDD2(C) |
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| connector 1208 to +5V. Check the following voltages : |
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| 8 | 9 | 10 | 11 | 4 | 14 5 | 17 | 33 | 50 58 | 52 | 57 |
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| R1 | 12 |
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| PRE- |
| CONTROL |
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| ADC |
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| R2 | 13 |
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| PROCESSING | FUNCTION |
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Point |
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| OUTPUT | 55 | ||
Position 1000 pins 1,3 | +5V ± 5% |
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| STAGES | FO | |
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| Vref |
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Position 7000 pins 5,17,21,57 | +3.3V ± 5% | VRIN | 7 |
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| SL | |||
| GENERATOR |
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| CONTROL |
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Position 7005 pin 14 | +5V ± 5% |
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| 40 |
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Position 7020 pins 25 |
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+5V ± 5% | SCL |
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| LDON | |||
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Position 7020 pins 26,27,28 | +10 ±10% | SDA | 39 | MICROCONTROLLER |
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Position 7021 pin 5 | +12V ±10 | RAB | 41 |
| INTERFACE |
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| MOTOR | ||||||
| 42 |
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Position 7022 pin 5 | +12V ±10 | SILD |
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| CONTROL | 60 | ||
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Position 7025 pin 16 | +5V ± 5% | HFIN | 2 |
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| DIGITAL |
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| ERROR |
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Position 7202 pin 38 | +5V ± 5% ( other appl. 3V3 possible) | HFREF | 1 |
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| PLL |
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| CORRECTOR |
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Position 7309 pins 4,13 | +3V3 ± 5% | ISLICE | END |
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Iref | 6 |
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Position 7120 pin 8 | +12V ± 10 |
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| EFM |
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| CL96532086_049.eps | TEST1 | 25 |
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| DEMODULATOR |
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| AUDIO |
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| PROCESSOR | EBU | 51 | |||
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| TEST2 | 31 | TEST |
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| INTERFACE | DOBM | ||
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| TEST3 | 44 |
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| SRAM |
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| EF | ||
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| SERIAL | SCLK | ||
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| CRIN | 16 |
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| DATA | 28 |
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| INTERFACE | WCLK | |
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| CROUT | 15 | TIMING |
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| RAM |
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8.3.2 | Clock Signals |
| CL16 | 26 |
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| DATA | ||
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| ADDRESSER |
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| CL11/4 | 49 |
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| SERIAL | ||
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| SCLI | |
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| DATA | 35 |
| Description |
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| (LOOPBACK) | WCLI |
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| The microprocessor has its own Xtal or resonator of 12MHz. |
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| INTERFACE | SDI | ||
| SFSY | 47 |
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| SUBCODE |
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| The CD10 needs a clock of 8.4672MHz + 100ppm. This speed | SUB | 46 |
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| PEAK |
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| PROCESSOR |
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| also relates to the disc speed. To avoid locking problems | RCK | 45 |
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| DETECT |
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| Vneg | ||
| between the two drives in the CDR775, both drives run on the |
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| Vpos | ||
| same clock. Therefore the CD main board gets the clock for the |
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| BITSTREAM 18 | ||
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| DECODER |
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| DAC | LN | ||||
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| decoder from the CDR main board via pin 2 of connector 1208. |
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| STATUS | 43 | MICRO- |
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| CONTROLLER |
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| VERSATILE PINS |
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| The DAC needs a system clock to drive its internal digital filters |
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| INTERFACE |
| KILL |
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| and to clock the I2S signals from the decoder. In our case this |
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| is 11.2896MHz (CL11) generated by the CD10. | RESET |
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| V1 | V2/ | V4 | V5 |
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| KILL | CL96532086_051.eps | |
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| V3 |
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| Connect the power supply as described above in "1.1.1. |
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| Supply Voltages". |
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| Figure |
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