Cypress CY7C1246V18 manuals
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Cypress CY7C1246V18 Manual
27 pages 642.76 Kb
CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)Features Configurations Functional Description Selection Guide 2 CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18Document Number: 001-06348 Rev. *D Page 2 of 27 Logic Block Diagram (CY7C1246V18) Logic Block Diagram (CY7C1257V18)2M x 8 Array 2M x 8 Array 2M x 9 Array 2M x 9 Array Document Number: 001-06348 Rev. *D Page 3 of 27 3 Logic Block Diagram (CY7C1248V18)Logic Block Diagram (CY7C1250V18)1M x 18 Array 1M x 18 Array 512K x 36 Array 512K x 36 Array 4 CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18Pin ConfigurationsCY7C1246V18 (4M x 8) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout 5 CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18Pin ConfigurationsCY7C1248V18 (2M x 18) 165-Ball FBGA (15 x 17 x 1.4 mm) Pinout 6 CY7C1246V18, CY7C1257V187 CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V188 CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18Functional OverviewRead Operations Write Operations Byte Write Operations Double Data Rate Operation Depth Expansion Programmable Impedance Echo Clocks Valid Data Indicator (QVLD) Delay Lock Loop (DLL) 9 Application ExampleTruth TableBUS MASTER (CPU or ASIC) SRAM#1 SRAM#2 12 CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18IEEE 1149.1 Serial Boundary Scan (JTAG)Disabling the JTAG Feature Test Access Port Test Clock Test Mode Select Test Data-In (TDI) Test Data-Out (TDO) Performing a TAP Reset TAP Re gist ers TAP Instruction Set 14 TAP Controller State DiagramTAP Controller Block Diagram 15 TAP Controller18 CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18Boundary Scan Order 19 Power Up Sequence in DDR-II+ SRAMPower Up SequenceClock Start (Clock Starts after VDD/VDDQ is Stable) Fix HIGH (tie to VDDQ) DLL Constraints Power Up WaveformsK K VDD/VDDQ DOFFUnstable Clock > 2048 Stable Clock Start Normal Operation VDD/VDDQ Stable (< + 0.1V DC per 50 ns) 20 Maximum Ratings Operating Range Electrical Characteristics DC Electrical Characteristics AC Input Requirements 21 CapacitanceThermal Resistance AC Test Loads and Waveforms 22 Switching CharacteristicsDocument Number: 001-06348 Rev. *D Page 23 of 27 23 Switching WaveformsRead/Write/Deselect SequenceREAD NOP WRITE READ READ 12345678910Figure 5. Waveform for 2.0 Cycle Read Latency WRITE 11 NOP NOP 24 CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V1825 CY7C1246V18, CY7C1257V18 CY7C1248V18, CY7C1250V18
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