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Advantech PCI-1718 Series user manual

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Contents

Main Page Page Page Contents Chapter 1 Introduction..................................................... 2 Chapter 2 Installation..................................................... 12 Chapter 3 Signal Connections........................................ 20 Chapter 4 Programming Guide ..................................... 38 Appendix A Specifications ................................................. 52 Appendix D Calibration..................................................... 82 Page Introduction Chapter 1 Introduction 1.1 Features 1.2 Applications 1.3 Installation Guide Page 1.4 Software Overview 1.5 Device Driver Programming Roadmap Page 1.6 Accessories Installation Chapter 2 Installation 2.1 Unpacking 2.2 Driver Installation Page 2.3 Hardware Installation 2.4 Device Setup & Configuration Page Page Signal Connections Chapter 3 Signal Connections 3.1 Overview 3.2 Switch and Jumper Settings 3.2.1 Setting the BoardID Switch (SW1) 3.2.2 Channel Configuration, S/E or DIFF (SW2) 3.2.3 D/A Reference Voltage, int./ext. (JP11) 3.2.4 Internal Voltage Reference, -10 V or -5 V (JP10) 3.2.5 Timer Clock Selection (JP8) 3.2.6 Ext. trigger and Counter Gate 0 Control (JP5) 3.2.7 Digital Output, 20-pin or 37-pin Connector (JP1) Table 3.7: Summary of Jumper Settings 3.2.8 Setting the Time to Reset Digital Outputs 3.3 Signal Connections 3.3.1 I/O Connector Signal Description Table 3.9: I/O Connector Signal Descriptions 3.3.2 Analog Input Connections Page Page Page 3.3.3 Digital Signal Connections 3.4 Field Wiring Considerations Page Programming Guide Chapter 4 Programming Guide 4.1 Overview 4.2 Programming with the Driver 4.3 Register Programming. 4.3.1 Software Trigger and Polling Page 41 Chapter 4 4.3.2 Pacer Trigger Mode with Interrupt Page Page Page 45 Chapter 4 4.3.3 Pacer Trigger Mode with Interrupt and FIFO Page Page Page 4.4 Programming with LabVIEW and ActiveDAQ Page Page Appendix A Specifications A.1 Analog Input A.2 Analog Output A.3 Digital Input A.4 Digital Output A.5 Counter/Timer A.6 General Page Page Page Page Appendix C Register Structure & Format C.1 Overview C.2 I/O Port Address Map Table C.1: PCI-1718HDU/HGU Register Format (Part 1) Table C.2: PCI-1718HDU/HGU Register Format (Part 2) Table C.3: PCI-1718HDU/HGU Register Format (Part 3) C.3 A/D Data and Channels BASE+00H~01H C.4 Software A/D Trigger BASE+00H C.5 A/D Range Control BASE+01H Note: G3 and G2 are not used for PCL-818L C.6 MUX Scan Channel Control BASE+02H C.7 MUX Scan Channel Status BASE+02H C.8 Digital I/O Registers - BASE + 03/0BH C.9 D/A Output BASE+04/05H C.10 FIFO Interrupt Control BASE+06H C.11 Clear Interrupt Request BASE+08H C.12 A/D Status BASE+08H Page C.13 A/D Control BASE+09H C.14 Timer/Counter Enable BASE+0AH C.15 Programmable Timer/Counter BASE+0C~0FH C.16 Clear FIFO Interrupt Request BASE+14H C.17 A/D Data and Channel from FIFO - BASE + 17/18H C.18 FIFO Status BASE+19H C.19 FIFO Clear BASE+19H 77 Appendix C C.20 Register Programming Flow Chart C.20.1 Software Trigger Mode with Polling PCI-1718 Series User Manual 78 C.20.2 Pacer Trigger Mode with Interrupt 79 Appendix C C.20.3 Pacer Trigger Mode with Interrupt [FIFO Used] Page Page Appendix D Calibration D.1 VR Assignment D.2 A/D Calibration D.3 D/A Calibration