Advantech PCI-1718 Series user manual Appendix Specifications

		3.3.2	Table 3.9:I/O Connector Signal Descriptions	29
			Analog Input Connections	30
			Figure 3.3:Analog Output Connections	33
		3.3.3	Digital Signal Connections	34
	3.4	Field Wiring Considerations		35
Chapter	4	Programming Guide		38
	4.1	Overview		38
	4.2	Programming with the Driver		38
	4.3	Register Programming		38
		4.3.1 Software Trigger and Polling		39
		4.3.2 Pacer Trigger Mode with Interrupt		41
		4.3.3 Pacer Trigger Mode with Interrupt and FIFO		45
	4.4	Programming with LabVIEW and ActiveDAQ		49
Appendix	A	Specifications		52
	A.1	Analog Input		52
	A.2	Analog Output		53
	A.3	Digital Input		53
	A.4	Digital Output		54
	A.5	Counter/Timer		54
	A.6	General		55
Appendix	B	Block Diagrams		58
Appendix C		Register Structure & Format		60
	C.1	Overview		60
	C.2	I/O Port Address Map		60
			Table C.1:PCI-1718HDU/HGU Reg. Format (Part 1)	61
			Table C.2:PCI-1718HDU/HGU Reg. Format (Part 2)	62
	C.3		Table C.3:PCI-1718HDU/HGU Reg. Format (Part 3)	63
		A/D Data and Channels — BASE+00H~01H		64
	C.4		Table C.4:Register for A/D Data and Channels	64
		Software A/D Trigger — BASE+00H		64
	C.5		Table C.5:Register for Software A/D Trigger	64
		A/D Range Control — BASE+01H		65
	C.6		Table C.6:Register for A/D Range Control	65
		MUX Scan Channel Control — BASE+02H		67
	C.7		Table C.7:Register for MUX Scan Channel Control ...	67
		MUX Scan Channel Status — BASE+02H		68
	C.8		Table C.8:Register for MUX Scan Channel Status	68
		Digital I/O Registers - BASE + 03/0BH		68
			Table C.9:Register for Digital Output	68
	C.9		Table C.10:Register for Digital Output	69
		D/A Output — BASE+04/05H		69
C.10			Table C.11:Register for D/A Output	69
		FIFO Interrupt Control — BASE+06H		70
C.11			Table C.12:Register for FIFO Interrupt Control	70
		Clear Interrupt Request — BASE+08H		71
C.12			Table C.13:Register for Clear Interrupt Request	71
		A/D Status — BASE+08H		71
			Table C.14:Register for A/D Status	71

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