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Advantech PCI-1718 Series user manual Pacer Trigger Mode with Interrupt, Isr

Models: PCI-1718 Series

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4.3.2 Pacer Trigger Mode with Interrupt

Set to Software Trigger Mode To Disable Trigger.

MUX Scan

Channel Control &

A/D Range

Control

Set Scan Channel

Set Pacer Rate

Set ISR

w Base+ 09H

w Base+0 2H w Base+0 1H

w Base+0 2H

Base+0 CH~ Base+0FH

ISR

Get Data

Clear Device

Interrupt Request

Clear System

Device Interrupt

End of ISR

Stop ISR

r Base+ 00H r Base+01H

w Base+ 08H

Set To Pacer

Trigger Mode and

Enable Device

Interrupt

Enable System To Accept Interrupt

Clear Device

Interrupt Request

Clear System Interrupt Request

Set To Pacer

Trigger Mode To

Enable Trigger

System Ready For Data Acquisition

w Base+ 09H

w Base+ 08H

w Base+ 09H

Set To Software

Trigger Mode To

Disable Trigger

Restore ISR

Disable Generated

Interrupt

Disable System

To Accept

Interrupt

w Base+0 9H

w Base+0 9H

Interrupt

41

Chapter4

Image 49

Advantech PCI-1718 Series user manual Pacer Trigger Mode with Interrupt, Isr

Contents

Bit Multifunction Cards with Universal PCI Bus PCI-1718 SeriesCopyright Acknowledgements Product Warranty 2 years Technical Support and Assistance Safety Precaution Static ElectricityPacking List Contents Appendix Specifications Appendix D Calibration Viii Introduction PCI-1718HDU/HGU is register-level- pro PCI-Bus Plug & Play FeaturesAutomatic Channel/Gain Scanning BoardID Switch Onboard Programmable Timer/CounterApplications Onboard FifoInstallation Guide Installation Flow Chart Programming choices for DA&C cards Software OverviewDevice Drivers Register-level ProgrammingProgramming Tools Device Driver Programming RoadmapProgramming with Device Drivers Function Library Troubleshooting Device Drivers ErrorWiring Cables PCL-10120 AccessoriesWiring Boards PCL-10137Installation Unpacking SETUP.EXE on the companion CD-ROM Driver InstallationSetup Screen of Advantech Automation Software Installation Hardware InstallationSetting Up the Device Device Setup & ConfigurationDevice Setting Dialog Box Configuring the DeviceTest Utility Dialog Box Signal Connections Overview Switch and Jumper SettingsBoard ID Setting SW1 Setting the BoardID Switch SW1Summary of Switch SW2 Settings Channel Configuration, S/E or Diff SW2Summary of Jumper JP11 Settings 3 D/A Reference Voltage, int./ext. JP11Internal Voltage Reference, -10 V or -5 V JP10 Summary of Jumper JP10 SettingsSummary of Jumper JP8 Settings Timer Clock Selection JP8Summary of Jumper Settings Digital Output, 20-pin or 37-pin Connector JP16 Ext. trigger and Counter Gate 0 Control JP5 JP1 first JP21 Jumper Settings Setting the Time to Reset Digital OutputsPin Assignment Signal ConnectionsI/O Connector Signal Descriptions 1 I/O Connector Signal DescriptionSingle-ended Channel Connections Analog Input ConnectionsDifferential Channel Connections Incorrect Connection Correct ConnectionExpanding Analog Inputs Analog Output Connections Analog Output ConnectionGND D.GND Digital Signal ConnectionsField Wiring Considerations Page Programming Guide Register Programming Programming with the DriverEOC=0 Software Trigger and PollingExample Code ISR Pacer Trigger Mode with InterruptExample Code Page Enable Pacer Trigger Mode with Interrupt and Fifo Add you code here Clear System Interrupt*****/ Add you code here Add your code here LabView Programming with LabVIEW and ActiveDAQActiveDAQ Page Specifications Analog Input Appendix a SpecificationsDigital Input Analog OutputDigital Output Counter/TimerGeneral Page Block Diagrams Appendix B Block Diagrams Register Structure & Format I/O Port Address Map Appendix C Register Structure & FormatTable C.1 PCI-1718HDU/HGU Register Format Part Table C.2 PCI-1718HDU/HGU Register Format Part Table C.3 PCI-1718HDU/HGU Register Format Part Software A/D Trigger BASE+00H A/D Data and Channels BASE+00H~01HTable C.5 Register for Software A/D Trigger PCI-1718HDU A/D Range Control BASE+01HG3 and G2 are not used for PCL-818L Table C.7 Register for MUX Scan Channel Control MUX Scan Channel Control BASE+02HProgramming example for PCI-1718HDU Digital I/O Registers Base + 03/0BH MUX Scan Channel Status BASE+02HTable C.8 Register for MUX Scan Channel Status Table C.9 Register for Digital OutputTable C.10 Register for Digital Output D/A Output BASE+04/05HTable C.11 Register for D/A Output Table C.12 Register for Fifo Interrupt Control Fifo Interrupt Control BASE+06H12 A/D Status BASE+08H Clear Interrupt Request BASE+08HTable C.13 Register for Clear Interrupt Request Table C.14 Register for A/D StatusMUX Table C.15 Register for A/D Control 13 A/D Control BASE+09HProgrammable Timer/Counter BASE+0C~0FH Timer/Counter Enable BASE+0AHTable C.16 Register for Timer/Counter Enable 17 A/D Data and Channel from Fifo Base + 17/18H Clear Fifo Interrupt Request BASE+14HTable C.17 Register for Clear Fifo Interrupt Request Table C.18 Register for A/D Data and Channel from FifoFifo Clear BASE+19H Fifo Status BASE+19HTable C.19 Register for Fifo Status Table C.20 Register for Fifo ClearSoftware Trigger Mode with Polling Register Programming Flow ChartPacer Trigger Mode with Interrupt Pacer Trigger Mode with Interrupt Fifo Used Page Calibration Appendix D Calibration Figure D.1 PCI-1718 VR Assignment VR AssignmentOutputs is recommended A/D CalibrationD/A Calibration