vii
C.13 A/D Control — BASE+09H ...........................................73
Table C.15:Register for A/D Control ......................... 73
C.14 Timer/Counter Enable — BASE+0AH........................... 74
Table C.16:Register for Timer/Counter Enable ........... 74
C.15 Programmable Timer/Counter — BASE+0C~0FH........ 74
C.16 Clear FIFO Interrupt Request — BASE+14H................ 75
Table C.17:Register for Clear FIFO Interrupt Request 75
C.17 A/D Data and Channel from FIFO - BASE + 17/18H.... 75
Table C.18:Register for A/D Data and Channel from
FIFO ................................................................. 75
C.18 FIFO Status — BASE+19H............................................ 76
Table C.19:Register for FIFO Status ............ ...............76
C.19 FIFO Clear — BASE+19H............................................. 76
Table C.20:Register for FIFO Clear ............................ 76
C.20 Register Programming Flow Chart .................................77
C.20.1 Software Trigger Mode with Polling ........................... 77
C.20.2 Pacer Trigger Mode with Interrupt .............................. 78
C.20.3 Pacer Trigger Mode with Interrupt [FIFO Used] .........79
Appendix D Calibration..................................................... 82D.1 VR Assignment .............................................................. 83
Figure D.1:PCI-1718 VR Assignment .........................83
D.2 A/D Calibration...............................................................84
D.3 D/A Calibration...............................................................85