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CY7C1006D, CY7C106D manual
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Contents
Main
1-Mbit (256K x 4) Static RAM
CY7C106D CY7C1006D
Features
Functional Description
Logic Block Diagram
Pin Configuration
Top Vie w
Selection Guide
SOJ
Maximum Ratings
Operating Range
Electrical Characteristics
Capacitance
Thermal Resistance
AC Test Loads and Waveforms
Switching Characteristics
CY7C106D CY7C1006D
Data Retention Characteristics
Read Cycle No. 2 (OE Controlled) [16, 17]
3mA tCDR [4] Chip Deselect to Data Retention Time 0 ns tR [13, 14] Operation Recovery Time tRC ns
Data Retention Waveform
CY7C106D CY7C1006D
Write Cycle No. 1 (CE Controlled) [18, 19]
Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [18, 19]
Switching Waveforms
Truth Table
Ordering Information
Switching Waveforms
Document #: 38-05459 Rev. *E Page 9 of 11
Package Diagrams
Figure 1. 28-pin (300-Mil) Molded SOJ, 51-85031
A
CY7C106D CY7C1006D
Figure 2. 28-pin (400-Mil) Molded SOJ, 51-85032
Package Diagrams
Document History Page