Acer ASX1200, ASX3200 manual Advanced Chipset Features, Auto, 100

Advanced Chipset Features

Parameter	Description	Option
Hyper SLI	Enable or disable the Scalable Link Interface (SLI) technology.	Disabled
		Enabled
iGPU Frame Buffer Control	When set to auto, BIOS will automatically setup the frame buffer size.	Auto
	When set to manual, you can set the frame buffer size. Frame buffer	Manual
	size is the total amount of system memory allocated solely for the
	onboard graphics controller.
Frame Buffer Size	This parameter can be configured if the iGPU Frame Buffer Control is	64, 16, 32, 128,
	set to Manual.	256 MB
CPU Frequency	Sets processor minimum and maximum frequency.	200
		Minimum 100
		Maximum 500
KB<->NB HT Speed	Controls the physical speed of the processor to the Northbridge HT link.	Auto
		200, 400, 600, 800
		MHz, 1 GHz
KB<->NB HT Width	Controls the processor to the Northbridge link bandwidth.	Auto
		Up 8/16
		Down 8/16
PCIE Clock	Sets the PCI Express clock frequency.	100
		Minimum 100
		Maximum 200
DRAM Configuration	Press Enter to configure memory timing and operation settings.
CPU Spread Spectrum	Allows you to reduce the EMI of the front side bus by modulating the	Disabled
	signals it generates so that the spikes are reduced to flatter curves.	-0.5%, 1.0%
PCIE Spread Spectrum	Allows you to reduce the EMI of the PCI Express bus by modulating the	Disabled
	signals it generates so that the spikes are reduced to flatter curves.	Down Spread
	When set to down spread, the chipset modulates the PCI Express bus'
	baseline signal downwards by a small amount.
	When set to disabled, the chipset disables any modulation of the PCI
	Express bus' baseline signal.
SATA Spread Spectrum	Allows you to reduce the EMI of the SATA bus by modulating the	Disabled
	signals it generates so that the spikes are reduced to flatter curves.	Down Spread
	When set to down spread, the chipset modulates the SATA bus'
	baseline signal downwards by a small amount.
	When set to disabled, the chipset disables any modulation of the SATA
	bus' baseline signal.

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