DRAM Configuration
Parameter | Description | Option |
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Timing Mode | When set to auto mode, the system reads the electronic data sheet of the | Auto |
| memory modules and adjusts the timings accordingly. | MaxMemClk |
| When set to MaxMemClk, you can manually specify the memory clock |
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| frequency independent of the system bus frequency. |
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Memory Clock value or Limit | Displays the current memory clock frequency. |
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CKE base power down | All synchronous memory devices can go into sleep mode as soon as the | Disabled |
mode | clock enable (CKE) signal is disasserted. In that case, the internal clocks are | Enabled |
| disabled and the memory chip goes into |
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| lowest power state at which the memory retains data. |
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| If then power is turned off, the device will lose all data, however, as long as |
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| standby power is maintained, no data loss will occur. |
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CKE based power down | Sets the CKE power saving through disasserting clock enable using system | Per Channel |
| level or per channel basis. | Per CS |
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Memclock | Enables or disables the memory clock | Disabled |
| feature. | Memclock tri- |
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| stating during |
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| C3 and Alt VD |
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Memory Hole Remapping | Enables or disables memory remapping around the memory hole. | Enabled |
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| Disabled |
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Auto Optimize Bottom IO | Allows you to auto optimize maximal memory size when kernel assigns PCI | Enabled |
| Resources. | Disabled |
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Bottom of UMA DRAM | Allows you to enter a HEX number ranging from 0000 to 00F0. | Minimim 0000 |
[31:24] [FC] |
| Maximum 00FC |
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Chapter 2 | 17 |
