1-24 Service Guide

Table 1-13 GPIO Port Definition Map II
GPIO I/O Description
P2.0 INC
P2.1 ONC
P2.2 (SM5_BAYSW) IDetect FDD/CD bay installed or not
P2.3 ONC
P2.4 ONC
P2.5 ONC
P2.6 ONC
P2.7 ONC
P3.0 (SM5_RXD) IReceiving data from KBC to SMC
P3.1 (SM5_TXD) OTransmitting data from SMC to KBC
P3.2 (SM5_DOCKSW) IDock switch sense
P3.3 (CF5_DOCKED) IDetect completely docked or not
P3.4 (SM5_LIDSW) ILid switch sense
P3.5 (SM5_OVTMP#) OCPU or system over temperature
P3.6 ONC
P3.7 (SM5_ON_RES_SW) OON/RESUME switch for Japan version
P4.0 (SM5_FANON) OFan control
P4.1 NC
P4.2 (SM5_FLOATREQ#) ODocking float request
P4.3 (SM5_UNDOCK_GNT#) OUndock grant
P4.4 (SM5_ICONT) ICharge current control
P4.5 (SM5_FLAOTGNT#) IDocking float grant
P4.6 (SM5_PWRRDYB) OPower ready, delay about 4ms after power good
P4.7 (SM5_SYSRDY) ONC
P5.0 (CHARGSP) ICharging set point
P5.1 (SM5_VBAT_MAIN) IMain battery detection
P5.2 (SM5_ACPWRGD) IAC source power good
P5.3 (SM5_NBPWRGD) I3V, 5V, processor module power good
P5.4 (SM5_ATFINT) ICPU thermal interrupt (panic)
P5.5 (SM5_THERM_SYS) ISystem thermal input (analog)
P5.6 (SM5_ACIN_AUX) IAux AC adapter in
P5.7 (SM5_ACIN_MAIN) IMain AC adapter in
PWM1# (SM5_CONT) OLCD contrast
PWM0# (SM5_BRIT) OLCD brightness
1.6.6 PCI Devices Assignment

Table 1-14 PCI Devices Assignment