Major Chips Description 2-21
Table 2-282371AB Pin Descriptions
Name Type Description
PIORDY IPRIMARY IO CHANNEL READY. In normal IDE mode, this input signal is
directly driven by the corresponding IDE device IORDY signal. In an Ultra
DMA/33 read cycle, this signal is used as STROBE, with the PIIX4 latching data
on rising and falling edges of STROBE. In an Ultra DMA/33 write cycle, this
signal is used as the DMARDY# signal which is negated by the drive to pause
Ultra DMA/33 transfers. If the IDE signals are configured for Primary and
Secondary, this signal is connected to the corresponding signal on the Primary
IDE connector. If the IDE signals are configured for Primary Master and Primary
Slave, this signal is used for the Primary Master connector. This is a Schmitt
triggered input.
SDA[2:0] OSECONDARY DISK ADDRESS[2:0]. These signals indicate which byte in either
the ATA command block or control block is being addressed. If the IDE signals
are configured for Primary and Secondary, these signals are connected to the
corresponding signals on the Secondary IDE connector. If the IDE signals are
configured for Primary Master and Primary Slave, these signals are used for the
Primary Slave connector.
During Reset: High-Z After Reset: Undefined During POS: SDA
SDCS1# OSECONDARY CHIP SELECT FOR 170H-177H RANGE. For ATA command
register block. If the IDE signals are configured for Primary and Secondary, this
output signal is connected to the corresponding signal on the Secondary IDE
connector. If the IDE signals are configured for Primary Master and Primary
Slave, these signals are used for the Primary Slave connector.
During Reset: High After Reset: High During POS: High
SDCS3# OSECONDARY CHIP SELECT FOR 370H-377H RANGE. For ATA control
register block. If the IDE signals are configured for Primary and Secondary, this
output signal is connected to the corresponding signal on the Secondary IDE
connector. If the IDE signals are configured for Primary Master and Primary
Slave, these signals are used for the Primary Slave connector.
During Reset: High After Reset: High During POS: High-Z
SDD[15:0] I/O SECONDARY DISK DATA[15:0]. These signals are used to transfer data to or
from the IDE device. If the IDE signals are configured for Primary and
Secondary, these signals are connected to the corresponding signals on the
Secondary IDE connector. If the IDE signals are configured for Primary Master
and Primary Slave, these signals are used for the Primary Slave connector.
During Reset: High-Z After Reset: Undefined During POS: SDD
SDDACK# OSECONDARY DMA ACKNOWLEDGE. This signal directly drives the IDE device
DMACK# signal. It is asserted by PIIX4 to indicate to IDE DMA slave devices
that a given data transfer cycle (assertion of SDIOR# or SDIOW#) is a DMA
data transfer cycle. This signal is used in conjunction with the PCI bus master
IDE function. It is not associated with any AT compatible DMA channel. If the
IDE signals are configured for Primary and Secondary, this signal is connected
to the corresponding signal on the Secondary IDE connector. If the IDE signals
are configured for Primary Master and Primary Slave, these signals are used for
the Primary Slave connector.
During Reset: High After Reset: High During POS: High