Agilent Technologies E8247C PSG CW, E8267C PSG, E8257C PSG manual 33. I/Q Inputs

Signal Generator Overview

Front Panel

33. I/Q INPUTS

These female BNC input connectors (E8267C only) accept an externally supplied, analog, I/Q modulation; the in-phase component is supplied through the I INPUT; the quadrature-phase component is supplied

through the Q INPUT. The signal level is = 0.5 Vrms for a calibrated output level. The nominal input

impedance is 50Ω or 600Ω . The damage level is 1 Vrms and 10 Vpeak. To activate signals applied to these connectors, press Mux > I/Q Source 1 or I/Q Source 2 and then select either Ext 50 Ohm or Ext 600 Ohm.On signal

generators with Option 1EM, these inputs are relocated to the rear panel.

34. DATA INPUT

This female BNC input connector (E8267C with Option 002/602 only) is CMOS compatible and accepts an externally supplied serial data input for digital modulation applications. The expected input is a 3.3 V CMOS signal (which is also TTL compatible) where a CMOS high = a data 1 and a CMOS low = a data 0. The maximum input data rate is 50 Mb/s. The data must be valid on the falling edges of the data clock (normal mode) or the on the falling edges of the symbol sync (symbol mode). The damage levels are

> +5.5 and < −0.5V. On signal generators with Option 1EM, this input is relocated to the rear panel.

35. DATA CLOCK INPUT

This female BNC input connector (E8267C only) is CMOS compatible and accepts an externally supplied data-clock input signal to synchronize serial data for use with the internal baseband generator (Option 002/602). The expected input is a 3.3 V CMOS bit clock signal (which is also TTL compatible) where the rising edge is aligned with the beginning data bit. The falling edge is used to clock the DATA and SYMBOL SYNC signals. The maximum clock rate is 50 MHz. The damage levels are > +5.5 and < −0.5V. On signal generators with Option 1EM, this input is relocated to the rear panel.

36. SYMBOL SYNC INPUT

This female BNC input connector (E8267C only) is CMOS compatible and accepts an externally supplied symbol sync signal for use with the internal baseband generator (Option 002/602). The expected input is a

3.3V CMOS bit clock signal (which is also TTL compatible). SYMBOL SYNC might occur once per

symbol or be a single one-bit-wide pulse that is used to synchronize the first bit of the first symbol. The maximum clock rate is 50 MHz. The damage levels are > +5.5 and < −0.5V. SYMBOL SYNC can be used

in two modes:

•When used as a symbol sync in conjunction with a data clock, the signal must be high during the first data bit of the symbol. The signal must be valid during the falling edge of the data clock signal and may be a single pulse or continuous.

•When the SYMBOL SYNC itself is used as the (symbol) clock, the CMOS falling edge is used to clock the DATA signal.

On signal generators with Option 1EM, this input is relocated to the rear panel.

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