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AMD 64 manual A.8.4 Node Interleaving Configuration in the BIOS, Appendix A

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40555 Rev. 3.00 June 2006	Performance Guidelines for AMD Athlon™ 64 and AMD Opteron™
	ccNUMA Multiprocessor Systems

A.8.4 Node Interleaving Configuration in the BIOS

AMD Opteron™ and Athlon™ 64 ccNUMA multiprocessor systems can be configured in the BIOS to interleave all memory across all nodes on a page basis (4KB for regular pages and 2M for large pages). Enabling node interleaving in the BIOS overrides the use of any tools and causes the OS to interleave all memory available to the system across all nodes in a round robin manner.

Appendix A

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AMD 64 manual A.8.4 Node Interleaving Configuration in the BIOS, Appendix A

Contents

Application Note Issue Date JunePerformance Guidelines for AMD Athlon 64 and AMD Opteron ccNUMA Multiprocessor SystemsTrademarks 2006 Advanced Micro Devices, Inc. All rights reservedChapter 3 Analysis and Recommendations ContentsChapter 2 Experimental Setup ContentsA.2.1 What Resources Are Used When a Single Read-Only or List of Figures List of Figures40555 Rev. 3.00 June List of FiguresPerformance Guidelines for AMD Athlon 64 and AMD Opteron ccNUMA Multiprocessor SystemsPerformance Guidelines for AMD Athlon 64 and AMD Opteron Revision HistoryRevision History ccNUMA Multiprocessor Systems40555 Rev. 3.00 June Revision HistoryPerformance Guidelines for AMD Athlon 64 and AMD Opteron ccNUMA Multiprocessor SystemsIntroduction Chapter 1 IntroductionChapter Introduction 1.1 Related DocumentsIntroduction 14 http//msdn2.microsoft.com/en-us/library/tt15eb9t.aspxChapter Chapter IntroductionPerformance Guidelines for AMD Athlon 64 and AMD Opteron ccNUMA Multiprocessor SystemsChapter Chapter 2 Experimental SetupExperimental Setup 2.1 System UsedExperimental Setup Figure 1. Quartet TopologyChapter 2.2 Synthetic TestFigure 2. Internal Resources Associated with a Quartet Node Experimental SetupExperimental Setup Data Access Rate QualifiersChapter 2.3 Reading and Interpreting Test Graphs2.3.1 X-Axis Display Experimental SetupExperimental Setup 2.3.2 Labels Used2.3.3 Y-Axis Display Analysis and Recommendations Chapter 3 Analysis and Recommendations3.1 Scheduling Threads 3.1.1 Multiple Threads-Independent DataAnalysis and Recommendations 3.2 Data Locality Considerations3.1.2 Multiple Threads-Shared Data 3.1.3 Scheduling on a Non-Idle System100% ChapterAnalysis and Recommendations 2 HopAnalysis and Recommendations 3.2.1 Keeping Data Local by Virtue of first TouchAnalysis and Recommendations ChapterAnalysis and Recommendations afterwords no longer needs the data structure and if only one of the worker threads needs the data structure. In other words, the data structure is not truly shared between the worker threads3.4.1 Myth All Equal Hop Cases Take Equal Time Threads access local data3.3 Avoid Cache Line Sharing 3.4 Common Hop Myths DebunkedAnalysis and Recommendations Threads firing at each other crossfireAnalysis and Recommendations Node 0 Core Node 1 Core Node 2 Core Node 3 CoreChapter Analysis and Recommendations Next, we increase the number of background threads to six, running on216% 3.4.2 Myth Greater Hop Distance Always Means Slower TimeChapter Analysis and RecommendationsAnalysis and Recommendations Both threads access memory on nodeAnalysis and Recommendations 0 hop-0 hop case for the write-only threadsChapter Analysis and Recommendations In addition, three background threads are running on nodes 1, 2 andHigh Total Time for both threads write-write ChapterAnalysis and Recommendations Medium Total Time for both threads write-write158% 158% 3.5 LocksAnalysis and Recommendations 147%Analysis and Recommendations ChapterChapter Analysis and RecommendationsPerformance Guidelines for AMD Athlon 64 and AMD Opteron ccNUMA Multiprocessor SystemsChapter Chapter 4 ConclusionsConclusions Conclusions Data placement tools can also come in handy when a thread needs more data than the amount of physical memory available on a node. Certain OSs also allow data migration with these tools or API. Using this feature, data can be migrated from the node where it was first touched to the node where it is subsequently accessed. There is a cost associated with this migration and it is not advised to use it frequently. For additional details on the tools and APIs offered by various OS for thread and memory placement refer to Section A.7 on pageAppendix A Appendix AA.1 Description of the Buffer Queues Figure 16. Internal Resources Associated with a Quartet NodePage Appendix A A.2.3 What Role Do Buffers Play in the Throughput Observed?0 Hop-1 Hop Case on an Idle System for Write- Only Threads? A.4 Why Is 0 Hop-0 Hop Case Slower Than theA.5 Why Is 0 Hop-1 Hop Case Slower Than Controlling Process and Thread Affinity A.7.1 Support Under LinuxAppendix A A.7.2 Support under SolarisA.7.3 Support under Microsoft Windows Controlling Memory AffinityA.8.3 Support under Microsoft Windows A.8.1 Support under LinuxA.8.2 Support under Solaris Appendix A A.8.4 Node Interleaving Configuration in the BIOS40555 Rev. 3.00 June Performance Guidelines for AMD Athlon 64 and AMD OpteronccNUMA Multiprocessor Systems Appendix A