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AMD manual Revision History, Performance Guidelines for AMD Athlon 64 and AMD Opteron

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Revision History

Performance Guidelines for AMD Athlon™ 64 and AMD Opteron™	40555 Rev. 3.00 June 2006
ccNUMA Multiprocessor Systems

8	Revision History

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AMD manual Revision History, Performance Guidelines for AMD Athlon 64 and AMD Opteron, ccNUMA Multiprocessor Systems

Contents

Issue Date June Performance Guidelines for AMD Athlon 64 andAMD Opteron ccNUMA Multiprocessor Systems Application Note2006 Advanced Micro Devices, Inc. All rights reserved TrademarksContents Chapter 2 Experimental SetupContents Chapter 3 Analysis and RecommendationsA.2.1 What Resources Are Used When a Single Read-Only or List of Figures List of FiguresList of Figures Performance Guidelines for AMD Athlon 64 and AMD OpteronccNUMA Multiprocessor Systems 40555 Rev. 3.00 JuneRevision History Revision HistoryccNUMA Multiprocessor Systems Performance Guidelines for AMD Athlon 64 and AMD OpteronRevision History Performance Guidelines for AMD Athlon 64 and AMD OpteronccNUMA Multiprocessor Systems 40555 Rev. 3.00 JuneIntroduction Chapter 1 IntroductionChapter Introduction 1.1 Related Documents10 http//msdn2.microsoft.com/en-us/library/ms186255SQL.90.aspx Introduction 14 http//msdn2.microsoft.com/en-us/library/tt15eb9t.aspxChapter Introduction Performance Guidelines for AMD Athlon 64 and AMD OpteronccNUMA Multiprocessor Systems ChapterChapter 2 Experimental Setup Experimental Setup2.1 System Used ChapterFigure 1. Quartet Topology Experimental Setup2.2 Synthetic Test Figure 2. Internal Resources Associated with a Quartet NodeExperimental Setup ChapterData Access Rate Qualifiers Experimental Setup2.3 Reading and Interpreting Test Graphs 2.3.1 X-Axis DisplayExperimental Setup ChapterExperimental Setup 2.3.2 Labels Used2.3.3 Y-Axis Display Chapter 3 Analysis and Recommendations 3.1 Scheduling Threads3.1.1 Multiple Threads-Independent Data Analysis and Recommendations3.2 Data Locality Considerations 3.1.2 Multiple Threads-Shared Data3.1.3 Scheduling on a Non-Idle System Analysis and RecommendationsChapter Analysis and Recommendations2 Hop 100%3.2.1 Keeping Data Local by Virtue of first Touch Analysis and RecommendationsChapter Analysis and Recommendationsafterwords no longer needs the data structure and if only one of the worker threads needs the data structure. In other words, the data structure is not truly shared between the worker threads Analysis and RecommendationsThreads access local data 3.3 Avoid Cache Line Sharing3.4 Common Hop Myths Debunked 3.4.1 Myth All Equal Hop Cases Take Equal TimeThreads firing at each other crossfire Analysis and RecommendationsAnalysis and Recommendations Node 0 Core Node 1 Core Node 2 Core Node 3 CoreChapter Next, we increase the number of background threads to six, running on Analysis and Recommendations3.4.2 Myth Greater Hop Distance Always Means Slower Time ChapterAnalysis and Recommendations 216%Both threads access memory on node Analysis and RecommendationsAnalysis and Recommendations 0 hop-0 hop case for the write-only threadsChapter In addition, three background threads are running on nodes 1, 2 and Analysis and RecommendationsChapter Analysis and RecommendationsMedium Total Time for both threads write-write High Total Time for both threads write-write3.5 Locks Analysis and Recommendations147% 158% 158%Chapter Analysis and RecommendationsAnalysis and Recommendations Performance Guidelines for AMD Athlon 64 and AMD OpteronccNUMA Multiprocessor Systems ChapterChapter Chapter 4 ConclusionsConclusions Data placement tools can also come in handy when a thread needs more data than the amount of physical memory available on a node. Certain OSs also allow data migration with these tools or API. Using this feature, data can be migrated from the node where it was first touched to the node where it is subsequently accessed. There is a cost associated with this migration and it is not advised to use it frequently. For additional details on the tools and APIs offered by various OS for thread and memory placement refer to Section A.7 on page ConclusionsAppendix A A.1 Description of the Buffer QueuesFigure 16. Internal Resources Associated with a Quartet Node Appendix APage A.2.3 What Role Do Buffers Play in the Throughput Observed? Appendix AA.4 Why Is 0 Hop-0 Hop Case Slower Than the 0 Hop-1 Hop Case on an Idle System for Write- Only Threads?A.5 Why Is 0 Hop-1 Hop Case Slower Than A.7.1 Support Under Linux Controlling Process and Thread AffinityA.7.2 Support under Solaris A.7.3 Support under Microsoft WindowsControlling Memory Affinity Appendix AA.8.3 Support under Microsoft Windows A.8.1 Support under LinuxA.8.2 Support under Solaris A.8.4 Node Interleaving Configuration in the BIOS Appendix APerformance Guidelines for AMD Athlon 64 and AMD Opteron ccNUMA Multiprocessor SystemsAppendix A 40555 Rev. 3.00 June