Preliminary Information
24332E— December 2002 | AMD Athlon™ Processor Model 6 Revision Guide |
1 Product Errata
This section documents AMD Athlon™ Processor Model 6 product errata. The errata are divided into categories to assist referencing particular errata. A unique tracking number for each erratum has been assigned within this document for user convenience in tracking the errata within specific revision levels. Table 1
Note: There can be missing errata numbers. Errata that have been resolved from early revisions of the processor have been deleted, and errata that have been reconsidered may have been deleted or renumbered.
Table 1. |
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| Revision |
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| Errata Numbers and Description |
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| A0 |
| A2 |
| A5 |
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16 INVLPG Instruction Does Not Flush Entire | X |
| X |
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Certain Linear Addresses |
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17 Deadlock May Occur in a | X |
| X |
| X | |
Memory- Mapped I/O |
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18 Processor May Issue | X |
| X |
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19 Processor Does Not Support Reliable Microcode Patch Mechanism |
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| X | |
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20 Processor Performance Counters Do Not Count Some x86 Instructions | X |
| X |
| X | |
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21 A Speculative SMC Store Followed by an Actual SMC Store May Cause One- | X |
| X |
| X | |
Time Stale Execution |
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22 Real Mode RDPMC with Illegal ECX May Cause Unpredictable Operation | X |
| X |
| X | |
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23 Using Task Gates With Breakpoints Enabled May Cause Unexpected Faults | X |
| X |
| X | |
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24 Single Step Across I/O SMI Skips One Debug Trap | X |
| X |
| X | |
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