Analog Devices 82-003536-01 manual Index, Getting Started With SHARC Processors

Help system described, 3-14

for VisualDSP++, 2-9High-performance USB 2.0 JTAG

emulator (HPUSB), 2-55HP-USB (high-performance USB JTAG

emulator), 2-55

I

IBIS (I/O buffer information specification) defined, 3-8

models, 3-8

IDDE (integrated software development and debugging environment), 2-2

instruction set reference, 3-6integrated software development and

debugging environment. See IDDE I/O buffer information specification. See

IBIS

J

Joint Test Action Group. See JTAG JTAG emulators

defined, 2-54USB 1.1, 2-58USB 2.0, 2-55

JTAG (Joint Test Action Group), 2-54

K

Kaztek Engineering, courses provided, 3-5kernel. See VDK

L

licenses described, 2-13floating, 2-61

linker description file, 3-11loader, 3-11, 3-12

Index

M

manual

new in this edition, x manuals. See documentation MyAnalog.com

defined, xii

e-mail notifications for, xii

O

online Help. See Help system

operating systems, supporting VisualDSP, 2-4

P

PGO (profile-guided optimization), 2-8processors

anomalies lists, 3-7data sheets, 3-7selection charts, 3-2

processor specifications ADSP-2126x, 1-9ADSP-2136x/ADSP-2137x, 1-10ADSP-2146x, 1-11ADSP-2147x, 1-13ADSP-2187x, 1-15

processor support options, 3-1Analog Devices Web site, 3-1application notes, EE-Notes,3-3documentation, 3-5EngineerZone, 3-15LinkedIn, 3-16

SHARC processor web page, 3-2third-party developers, 3-15Twitter, 3-16

profile-guided optimization. See PGO

Getting Started With SHARC Processors I-3