Introduction to SHARC Processors
•An SDRAM controller that provides an interface to as many as four separate banks of
•Up to a maximum of 5M bits of
•Input/output processor (IOP) with integrated direct memory access (DMA) controller, serial peripheral interface (SPI) compati- ble port, and serial ports (SPORTs) for
•A variety of
•JTAG test access port for emulation
Figure
Four Generations of SHARC Processors
The SHARC architecture has a long history in the
Getting Started With SHARC Processors |